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nand flash memory mt29f32g08cbaca, mt29f64g08ceaca, mt29f64g08cfaca, MT29F128G08CXACA, mt29f64g08ceccb features ? open nand flash interface (onfi) 2.2-compliant 1 ? multiple-level cell (mlc) technology ? organization C page size x8: 4320 bytes (4096 + 224 bytes) C block size: 256 pages (1024k + 56k bytes) C plane size: 2 planes x 2048 blocks per plane C device size: 32gb: 4096 blocks; 64gb: 8192 blocks; 128gb: 16,384 blocks ? synchronous i/o performance C up to synchronous timing mode 5 C clock rate: 10ns (ddr) C read/write throughput per pin: 200 mt/s ? asynchronous i/o performance C up to asynchronous timing mode 5 C t rc/ t wc: 20ns (min) ? array performance C read page: 50s (max) C program page: 1300s (typ) C erase block: 3ms (typ) ? operating voltage range C v cc : 2.7C3.6v C v ccq : 1.7C1.95v, 2.7C3.6v ? command set: onfi nand flash protocol ? advanced command set C program cache C read cache sequential C read cache random C one-time programmable (otp) mode C multi-plane commands C multi-lun operations C read unique id C copyback ? first block (block address 00h) is valid when ship- ped from factory. for minimum required ecc, see error management (page 101). ? reset (ffh) required as first command after power- on ? operation status byte provides software method for detecting C operation completion C pass/fail condition C write-protect status ? data strobe (dqs) signals provide a hardware meth- od for synchronizing data dq in the synchronous interface ? copyback operations supported within the plane from which data is read ? quality and reliability C data retention: 10 years C endurance: 3000 program/erase cycles ? operating temperature: C commercial: 0c to +70c C industrial (it): C40oc to +85oc ? package C 52-pad lga C 48-pin tsop C 100-ball bga note: 1. the onfi 2.2 specification is available at www.onfi.org . micron confidential and proprietary advance ? 32gb, 64gb, 128gb asynchronous/synchronous nand features pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. ?products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron's production data sheet specifications. draft 03/25/10 free datasheet http://
part numbering information micron nand flash devices are available in different configurations and densities. verify valid part numbers by using microns part catalog search at www.micron.com . to compare features and specifications by device type, visit www.micron.com/products . contact the factory for devices not found. figure 1: part numbering mt 29f 32g 08 c b a c a wp es :c micron t echnology nand flash 29f = nand flash memory density 32g = 32gb 64g = 64gb 128g = 128gb device width 08 = 8 bits level bit/cell c 2-bit classification die # of ce# # of r/b# i/o b 1 1 1 common e 2 2 2 separate f 2 2 2 common x 4 4 2 separate operating v oltage range a = v cc : 3.3v (2.7C3.6v), v ccq : 3.3v (2.7C3.6v) c = v cc : 3.3v (2.7C3.6v), v ccq : 1.8v (1.7C1.95v) design revision c = third revision production status blank = production es = engineering sample reserved for future use blank operating t emperature range blank = commercial (0c to +70c) it = industrial (C40c to +85c) speed grade (synchronous mode only) 10 = 200 mt/s package code d1 = 52-pad vlga 11mm x 14mm x 0.9mm 1 h1 = 100-ball vbga 12mm x 18mm x 1.0mm 1 wp = 48-pin tsop 1 (cpl) interface a = async only b = sync/async generation feature set c = third set of device features note: 1. pb-free package. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand features pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
contents general description ......................................................................................................................................... 9 asynchronous and synchronous signal descriptions ......................................................................................... 9 signal assignments ......................................................................................................................................... 11 package dimensions ...................................................................................................................................... 14 architecture ................................................................................................................................................... 17 device and array organization ....................................................................................................................... 18 bus operation C asynchronous interface ........................................................................................................ 23 asynchronous enable/standby ................................................................................................................... 23 asynchronous bus idle ............................................................................................................................... 23 asynchronous commands .......................................................................................................................... 24 asynchronous addresses ............................................................................................................................ 25 asynchronous data input ........................................................................................................................... 26 asynchronous data output ........................................................................................................................ 27 write protect .............................................................................................................................................. 28 ready/busy# .............................................................................................................................................. 28 bus operation C synchronous interface ........................................................................................................... 33 synchronous enable/standby ..................................................................................................................... 34 synchronous bus idle/driving .................................................................................................................... 34 synchronous commands ........................................................................................................................... 35 synchronous addresses .............................................................................................................................. 36 synchronous ddr data input ..................................................................................................................... 37 synchronous ddr data output .................................................................................................................. 38 write protect .............................................................................................................................................. 40 ready/busy# .............................................................................................................................................. 40 device initialization ....................................................................................................................................... 41 activating interfaces ....................................................................................................................................... 42 activating the asynchronous interface ........................................................................................................ 42 activating the synchronous interface .......................................................................................................... 42 command definitions .................................................................................................................................... 44 reset operations ............................................................................................................................................ 46 reset (ffh) ............................................................................................................................................... 46 synchronous reset (fch) .................................................................................................................... 47 reset lun (fah) ....................................................................................................................................... 48 identification operations ................................................................................................................................ 49 read id (90h) ............................................................................................................................................ 49 read id parameter tables ............................................................................................................................. 50 configuration operations ............................................................................................................................... 51 set features (efh) ................................................................................................................................. 51 get features (eeh) ................................................................................................................................. 52 read parameter page (ech) ...................................................................................................................... 56 parameter page data structure tables ............................................................................................................. 57 read unique id (edh) ................................................................................................................................ 64 status operations ........................................................................................................................................... 65 read status (70h) ................................................................................................................................... 66 read status enhanced (78h) ............................................................................................................... 67 column address operations ........................................................................................................................... 68 change read column (05h-e0h) .......................................................................................................... 68 change read column enhanced (06h-e0h) ....................................................................................... 69 change write column (85h) ................................................................................................................ 70 change row address (85h) ................................................................................................................... 71 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
read operations ............................................................................................................................................. 73 read mode (00h) ..................................................................................................................................... 75 read page (00h-30h) ................................................................................................................................ 76 read page cache sequential (31h) ..................................................................................................... 77 read page cache random (00h-31h) .................................................................................................... 78 read page cache last (3fh) .................................................................................................................. 80 read page multi-plane (00h-32h) ........................................................................................................ 81 program operations ....................................................................................................................................... 83 program page (80h-10h) ........................................................................................................................ 83 program page cache (80h-15h) ............................................................................................................ 85 program page multi-plane 80h-11h ................................................................................................... 87 erase operations ............................................................................................................................................ 89 erase block (60h-d0h) ............................................................................................................................ 89 erase block multi-plane (60h-d1h) .................................................................................................... 90 copyback operations ..................................................................................................................................... 91 copyback read (00h-35h) ....................................................................................................................... 92 copyback program (85hC10h) ............................................................................................................... 93 copyback read multi-plane (00h-32h) ............................................................................................... 93 copyback program multi-plane (85h-11h) ........................................................................................ 94 one-time programmable (otp) operations .................................................................................................... 95 program otp page (80h-10h) ................................................................................................................. 96 protect otp area (80h-10h) ................................................................................................................... 97 read otp page (00h-30h) ......................................................................................................................... 98 multi-plane operations .................................................................................................................................. 99 multi-plane addressing .............................................................................................................................. 99 interleaved die (multi-lun) operations ........................................................................................................ 100 error management ........................................................................................................................................ 101 output drive impedance ............................................................................................................................... 102 ac overshoot/undershoot specifications ...................................................................................................... 105 synchronous input slew rate ........................................................................................................................ 106 output slew rate ........................................................................................................................................... 107 electrical specifications ................................................................................................................................. 108 electrical specifications C dc characteristics and operating conditions (asynchronous) ................................. 110 electrical specifications C dc characteristics and operating conditions (synchronous) .................................. 110 electrical specifications C dc characteristics and operating conditions (v ccq ) ............................................... 111 electrical specifications C ac characteristics and operating conditions (asynchronous) ................................. 112 electrical specifications C ac characteristics and operating conditions (synchronous) ................................... 114 electrical specifications C array characteristics .............................................................................................. 117 asynchronous interface timing diagrams ...................................................................................................... 118 synchronous interface timing diagrams ........................................................................................................ 129 revision history ............................................................................................................................................ 151 rev. a C 3/10 ............................................................................................................................................. 151 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
list of tables table 1: asynchronous and synchronous signal definitions ............................................................................. 9 table 2: array addressing for logical unit (lun) ............................................................................................ 22 table 3: asynchronous interface mode selection ........................................................................................... 23 table 4: synchronous interface mode selection ............................................................................................. 33 table 5: command set .................................................................................................................................. 44 table 6: read id parameters for address 00h ................................................................................................. 50 table 7: read id parameters for address 20h .................................................................................................. 50 table 8: feature address definitions .............................................................................................................. 51 table 9: feature address 01h: timing mode ................................................................................................... 53 table 10: feature addresses 10h and 80h: programmable output drive strength ............................................. 53 table 11: feature addresses 81h: programmable r/b# pull-down strength ..................................................... 54 table 12: feature addresses 90h: array operation mode ................................................................................. 54 table 13: parameter page data structure ....................................................................................................... 57 table 14: status register definition ............................................................................................................... 65 table 15: otp area details ............................................................................................................................ 96 table 16: error management details ............................................................................................................. 101 table 17: output drive strength test conditions (v ccq = 1.7C1.95v) .............................................................. 102 table 18: output drive strength impedance values (v ccq = 1.7C1.95v) .......................................................... 102 table 19: output drive strength conditions (v ccq = 2.7C3.6v) ....................................................................... 103 table 20: output drive strength impedance values (v ccq = 2.7C3.6v) ............................................................ 103 table 21: pull-up and pull-down output impedance mismatch .................................................................... 104 table 22: overshoot/undershoot parameters ................................................................................................ 105 table 23: test conditions for input slew rate ................................................................................................ 106 table 24: input slew rate (v ccq = 1.7C1.95v) ................................................................................................. 106 table 25: test conditions for output slew rate ............................................................................................. 107 table 26: output slew rate (v ccq = 1.7C1.95v) .............................................................................................. 107 table 27: output slew rate (v ccq = 2.7C3.6v) ................................................................................................ 107 table 28: absolute maximum ratings by device ............................................................................................ 108 table 29: recommended operating conditions ............................................................................................ 108 table 30: valid blocks per lun ..................................................................................................................... 108 table 31: capacitance: 100-ball bga package ................................................................................................ 109 table 32: capacitance: 48-pin tsop package ................................................................................................ 109 table 33: capacitance: 52-pad lga package .................................................................................................. 109 table 34: test conditions ............................................................................................................................. 109 table 35: dc characteristics and operating conditions (asynchronous interface) .......................................... 110 table 36: dc characteristics and operating conditions (synchronous interface) ........................................... 110 table 37: dc characteristics and operating conditions (3.3v v ccq ) ............................................................... 111 table 38: dc characteristics and operating conditions (1.8v v ccq ) ............................................................... 112 table 39: ac characteristics: asynchronous command, address, and data .................................................... 112 table 40: ac characteristics: synchronous command, address, and data ...................................................... 114 table 41: array characteristics ..................................................................................................................... 117 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
list of figures figure 1: part numbering ................................................................................................................................ 2 figure 2: 48-pin tsop type 1 (top view) ....................................................................................................... 11 figure 3: 52-pad lga (ball-down, top view) .................................................................................................. 12 figure 4: 100-ball bga (ball-down, top view) ................................................................................................ 13 figure 5: 48-pin tsop C type 1 cpl (package code: wp) ................................................................................ 14 figure 6: 52-pad vlga C 11mm x 14mm (package code: d1) ........................................................................... 15 figure 7: 100-ball vbga C 12mm x 18mm (package code: h1) ......................................................................... 16 figure 8: nand flash die (lun) functional block diagram ........................................................................... 17 figure 9: device organization for single-die package (tsop) ......................................................................... 18 figure 10: device organization for two-die package (tsop) .......................................................................... 19 figure 11: device organization for two-die package (bga/lga) .................................................................... 20 figure 12: device organization for four-die package with four ce# and two r/b# (lga) ................................. 21 figure 13: array organization per logical unit (lun) ..................................................................................... 22 figure 14: asynchronous command latch cycle ............................................................................................ 24 figure 15: asynchronous address latch cycle ................................................................................................ 25 figure 16: asynchronous data input cycles ................................................................................................... 26 figure 17: asynchronous data output cycles ................................................................................................. 27 figure 18: asynchronous data output cycles (edo mode) ............................................................................. 28 figure 19: read/busy# open drain ............................................................................................................. 29 figure 20: t fall and t rise (v ccq = 2.7-3.6v) ...................................................................................................... 30 figure 21: t fall and t rise (v ccq = 1.7-1.95v) .................................................................................................... 30 figure 22: iol vs rp (v ccq = 2.7-3.6v) ............................................................................................................ 31 figure 23: iol vs rp (v ccq = 1.7-1.95v) .......................................................................................................... 31 figure 24: tc vs rp ........................................................................................................................................ 32 figure 25: synchronous bus idle/driving behavior ......................................................................................... 35 figure 26: synchronous command cycle ....................................................................................................... 36 figure 27: synchronous address cycle ........................................................................................................... 37 figure 28: synchronous ddr data input cycles ............................................................................................. 38 figure 29: synchronous ddr data output cycles ........................................................................................... 40 figure 30: r/b# power-on behavior ............................................................................................................... 41 figure 31: activating the synchronous interface ............................................................................................. 43 figure 32: reset (ffh) operation ................................................................................................................. 46 figure 33: synchronous reset (fch) operation ....................................................................................... 47 figure 34: reset lun (fah) operation ......................................................................................................... 48 figure 35: read id (90h) with 00h address operation .................................................................................... 49 figure 36: read id (90h) with 20h address operation .................................................................................... 49 figure 37: set features (efh) operation .................................................................................................... 52 figure 38: get features (eeh) operation ................................................................................................... 52 figure 39: read parameter (ech) operation .............................................................................................. 56 figure 40: read unique id (edh) operation ............................................................................................... 64 figure 41: read status (70h) operation ...................................................................................................... 67 figure 42: read status enhanced (78h) operation .................................................................................. 67 figure 43: change read column (05h-e0h) operation ............................................................................. 68 figure 44: change read column enhanced (06h-e0h) operation ......................................................... 69 figure 45: change write column (85h) operation ................................................................................... 70 figure 46: change row address (85h) operation ..................................................................................... 72 figure 47: read page (00h-30h) operation ................................................................................................... 76 figure 48: read page cache sequential (31h) operation ........................................................................ 77 figure 49: read page cache random (00h-31h) operation ....................................................................... 79 figure 50: read page cache last (3fh) operation ..................................................................................... 80 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 51: read page multi-plane (00h-32h) operation ........................................................................... 82 figure 52: program page (80h-10h) operation ........................................................................................... 84 figure 53: program page cache (80hC15h) operation (start) .................................................................... 86 figure 54: program page cache (80hC15h) operation (end) ..................................................................... 86 figure 55: program page multi-plane (80hC11h) operation ................................................................... 88 figure 56: erase block (60h-d0h) operation .............................................................................................. 89 figure 57: erase block multi-plane (60hCd1h) operation ...................................................................... 90 figure 58: copyback read (00h-35h) operation .......................................................................................... 92 figure 59: copyback read (00hC35h) with change read column (05hCe0h) operation .......................... 92 figure 60: copyback program (85hC10h) operation .................................................................................. 93 figure 61: copyback program (85h-10h) with change write column (85h) operation ........................ 93 figure 62: copyback program multi-plane (85h-11h) operation ........................................................... 94 figure 63: program otp page (80h-10h) operation .................................................................................... 96 figure 64: program otp page (80h-10h) with change write column (85h) operation .......................... 97 figure 65: protect otp area (80h-10h) operation ..................................................................................... 98 figure 66: read otp page (00h-30h) operation ........................................................................................... 98 figure 67: overshoot .................................................................................................................................... 105 figure 68: undershoot ................................................................................................................................. 105 figure 69: reset operation ......................................................................................................................... 118 figure 70: reset lun operation .................................................................................................................. 118 figure 71: read status cycle ..................................................................................................................... 119 figure 72: read status enhanced cycle ................................................................................................. 119 figure 73: read parameter page ............................................................................................................. 120 figure 74: read page ................................................................................................................................. 120 figure 75: read page operation with ce# dont care ............................................................................... 121 figure 76: change read column ............................................................................................................ 122 figure 77: read page cache sequential ................................................................................................ 123 figure 78: read page cache random ..................................................................................................... 124 figure 79: read id operation ...................................................................................................................... 125 figure 80: program page operation .......................................................................................................... 125 figure 81: program page operation with ce# dont care ....................................................................... 126 figure 82: program page operation with change write column ........................................................ 126 figure 83: program page cache .............................................................................................................. 127 figure 84: program page cache ending on 15h ....................................................................................... 127 figure 85: copyback .................................................................................................................................. 128 figure 86: erase block operation .............................................................................................................. 128 figure 87: set features operation ............................................................................................................ 129 figure 88: read id operation ...................................................................................................................... 130 figure 89: get features operation ........................................................................................................... 131 figure 90: reset (fch) operation ................................................................................................................ 132 figure 91: read status cycle ..................................................................................................................... 133 figure 92: read status enhanced operation .......................................................................................... 134 figure 93: read parameter page operation ............................................................................................. 135 figure 94: read page operation ................................................................................................................. 136 figure 95: change read column ............................................................................................................ 137 figure 96: read page cache sequential (1 of 2) ..................................................................................... 138 figure 97: read page cache sequential (2 of 2) ..................................................................................... 139 figure 98: read page cache random (1 of 2) .......................................................................................... 140 figure 99: read page cache random (2 of 2) .......................................................................................... 140 figure 100: multi-plane read page (1 of 2) ..................................................................................................... 141 figure 101: multi-plane read page (2 of 2) ..................................................................................................... 142 figure 102: program page operation (1 of 2) ............................................................................................. 143 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 103: program page operation (2 of 2) ............................................................................................. 143 figure 104: change write column ......................................................................................................... 144 figure 105: multi-plane program page .......................................................................................................... 145 figure 106: erase block ............................................................................................................................ 146 figure 107: copyback (1 of 3) ..................................................................................................................... 146 figure 108: copyback (2 of 3) ..................................................................................................................... 147 figure 109: copyback (3 of 3) ..................................................................................................................... 147 figure 110: read otp page ........................................................................................................................ 148 figure 111: program otp page (1 of 2) ...................................................................................................... 149 figure 112: program otp page (2 of 2) ...................................................................................................... 149 figure 113: protect otp area .................................................................................................................. 150 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
general description micron nand flash devices include an asynchronous data interface for high-perform- ance i/o operations. these devices use a highly multiplexed 8-bit bus (dqx) to transfer commands, address, and data. there are five control signals used to implement the asyn- chronous data interface: ce#, cle, ale, we#, and re#. additional signals control hardware write protection (wp#) and monitor device status (r/b#). this micron nand flash device additionally includes a synchronous data interface for high-performance i/o operations. when the synchronous interface is active, we# be- comes clk and re# becomes w/r#. data transfers include a bidirectional data strobe (dqs). this hardware interface creates a low pin-count device with a standard pinout that re- mains the same from one density to another, enabling future upgrades to higher densi- ties with no board redesign. a target is the unit of memory accessed by a chip enable signal. a target contains one or more nand flash die. a nand flash die is the minimum unit that can independently execute commands and report status. a nand flash die, in the onfi specification, is referred to as a logical unit (lun). for further details, see device and array organization. asynchronous and synchronous signal descriptions table 1: asynchronous and synchronous signal definitions asynchronous signal 1 synchronous signal 1 type description 2 ale ale input address latch enable: loads an address from dqx into the address reg- ister. ce# ce# input chip enable: enables or disables one or more die (luns) in a target 1 . cle cle input command latch enable: loads a command from dqx into the com- mand register. dqx dqx i/o data inputs/outputs: the bidirectional i/os transfer address, data, and command information. C dqs i/o data strobe: provides a synchronous reference for data input and out- put. re# w/r# input read enable and write/read: re# transfers serial data from the nand flash to the host system when the asynchronous interface is active. when the synchronous interface is active, w/r# controls the direction of dqx and dqs. we# clk input write enable and clock: we# transfers commands, addresses, and seri- al data from the host system to the nand flash when the asynchronous interface is active. when the synchronous interface is active, clk latches command and address cycles. wp# wp# input write protect: enables or disables array program and erase opera- tions. r/b# r/b# output ready/busy: an open-drain, active-low output that requires an exter- nal pull-up resistor. this signal indicates target array activity. v cc v cc supply v cc : core power supply micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand general description pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 1: asynchronous and synchronous signal definitions (continued) asynchronous signal 1 synchronous signal 1 type description 2 v ccq v ccq supply v ccq : i/o power supply v ss v ss supply v ss : core ground connection v ssq v ssq supply v ssq : i/o ground connection nc nc C no connect: ncs are not internally connected. they can be driven or left unconnected. dnu dnu C do not use: dnus must be left unconnected. rfu rfu C reserved for future use: rfus must be left unconnected. notes: 1. see device and array organization for detailed signal connections. 2. see bus operation C asynchronous interface (page 23) and bus operation C synchro- nous interface (page 33) for detailed asynchronous and synchronous interface signal descriptions. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous and synchronous signal descriptions pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
signal assignments figure 2: 48-pin tsop type 1 (top view) sync x8 nc nc nc nc nc r/b2# 1 r/b# w/r# ce# ce2# 1 nc v cc v ss nc nc cle ale clk wp# nc nc nc nc nc async x8 nc nc nc nc nc r/b2# 1 r/b# re# ce# ce2# 1 nc v cc v ss nc nc cle ale we# wp# nc nc nc nc nc async x8 dnu/v ssq 2 nc nc nc dq7 dq6 dq5 dq4 nc dnu/v ccq 2 dnu v cc v ss dnu dnu/v ccq 2 nc dq3 dq2 dq1 dq0 nc nc dnu dnu/v ssq 2 sync x8 dnu/v ssq 2 nc nc nc dq7 dq6 dq5 dq4 nc dnu/v ccq 2 dnu v cc v ss dqs dnu/v ccq 2 nc dq3 dq2 dq1 dq0 nc nc dnu dnu/v ssq 2 1 l 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 notes: 1. ce2# and r/b2# are available on dual die packages. they are nc for other configurations. 2. these v ccq and v ssq pins are for compatibility with onfi 2.2. if not supplying v ccq or v ssq to these pins, do not use them. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand signal assignments pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 3: 52-pad lga (ball-down, top view) nc nc nc nc nc nc nc nc nc nc v ss nc nc ale-1 we#-2 dq0-2 dq1-2 dq2-2 v cc a b c d e f g h j k l m n v ss ale-2 ce4# 1 dq1-1 dq3-1 v ss cle-1 cle-2 we#-1 dq0-1 dq2-1 v ss dq3-2 ce# ce2# r/b# ce3# 1 dq6-1 dq4-1 dq4-2 v cc re#-2 v ss dq7-1 dq5-1 v cc nc re#-1 r/b2# dq7-2 dq6-2 dq5-2 v cc top view, pads down 0 1 2 3 4 5 6 7 8 note: 1. these signals are available on quad die packages. they are nc for other configurations. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand signal assignments pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 4: 100-ball bga (ball-down, top view) a b d e f g h j k l m n p t u a b d e f g h j k l m n p t u 2 nc rfu rfu v c c v ss v ssq dq0-2 3 dq0-1 v cc q dq1-2 3 dq1-1 v ssq nc 3 dnu dnu v c c v ss v cc q dq2-2 3 dq2-1 v ssq dq3-2 3 dq3-1 v cc q 4 nc nc v c c v ss rfu ale-2 3 ale-1 v cc q v ssq rfu rfu 5 wp#-2 3 wp#-1 v c c v ss rfu ce4# 4 ce3# 4 cle-2 3 cle-1 n/a 1 n/a 1 6 nc nc v c c v ss r/b2# 3 r/b# ce2# 3 re#-2 3 re#-1 rfu rfu 7 nc nc v c c v ss r/b4# 4 r/b3# 4 ce# v cc q v ssq we#-2 3 we#-1 8 dnu dnu v c c v ss v cc q dq5-2 3 dq5-1 v ssq dq4-2 3 dq4-1 v cc q 9 nc rfu rfu v c c v ss v ssq dq7-2 3 dq7-1 v cc q dq6-2 3 dq6-1 v ssq nc 1 nc nc nc nc 10 nc nc nc nc (w/r#-1) (w/r#-2) (clk-1) (clk-2) (dqs-1) 1 2 3 4 5 6 7 8 9 10 (dq s -2 3 ) notes: 1. n/a: this signal is tri-stated when the asynchronous interface is active. 2. signal names in parentheses are the signal names when the synchronous interface is active. 3. these signals are available on dual die packages. they are nc for other configurations. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand signal assignments pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
package dimensions figure 5: 48-pin tsop C type 1 cpl (package code: wp) 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 for reference only 0.50 typ for reference only 12.00 0.08 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side. note: 1. all dimensions are in millimeters. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand package dimensions pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 6: 52-pad vlga C 11mm x 14mm (package code: d1) seating plane see detail b a a section a-a detail b not to scale 0.1 a a 0.9 max overall/max package height shall include package bow. 2 11 0.1 9 ctr 40x ?0.7 1 12x ?1 1 4 ctr 6 ctr 12 ctr 10 ctr 2 typ 14 0.1 terminal a1 id terminal a1 id see note 1 see note 2 2 ctr notes: 1. pads are nonsolder mask defined (nsmd), plated with 3C15m of nickel, and finished with a minimum of 0.1m of soft wire bondable gold. 2. total warpage (convex or concave) to be less than or equal to 75m from room temperature through 260c and back to room temperature. 8 7 6 5 4 3 2 1 0 a b c d e f g h j k l m n mold compound: epoxy novolac substrate material: plastic laminate notes: 1. primary datum a (seating plane) is defined by the bottom terminal surface. metallized test terminal lands or interconnect terminals need not extend below the package bot- tom surface. 2. all dimensions are in millimeters. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand package dimensions pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 7: 100-ball vbga C 12mm x 18mm (package code: h1) ball a1 id ball a1 id 0.12 a a 0.63 0.05 100x ?0.45 solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). dimensions apply to solder balls post-reflow on ?0.4 smd ball pads. 16 ctr 8 7 18 0.1 1 typ 1 typ 1 typ 9 ctr 12 0.1 1.0 max bottom side saw fiducials may or may not be covered with soldermask. 0.25 min seating plane 10 9 8 7 6 5 4 3 2 1 a b d e f g h j k l m n p t u note: 1. all dimensions are in millimeters. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand package dimensions pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
architecture these devices use nand flash electrical and command interfaces. data, commands, and addresses are multiplexed onto the same pins and received by i/o control circuits. the commands received at the i/o control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control de- vice operations. the addresses are latched by an address register and sent to a row decoder to select a row address, or to a column decoder to select a column address. data is transferred to or from the nand flash memory array, byte by byte, through a data register and a cache register. the nand flash memory array is programmed and read using page-based operations and is erased using block-based operations. during normal page operations, the data and cache registers act as a single register. during cache operations, the data and cache registers operate independently to increase data throughput. the status register reports the status of die (lun) operations. figure 8: nand flash die (lun) functional block diagram status register command register vccq vssq ce# cle n/a ale re# wp# dq[7:0] async we# r/b# ce# cle dqs ale w/r# wp# dq[7:0] sync clk r/b# vcc vss control logic data register cache register row decode column decode nand flash array data register cache register row decode column decode nand flash array (2 planes) address register i/o control notes: 1. n/a: this signal is tri-stated when the asynchronous interface is active. 2. some devices do not include the synchronous interface. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand architecture pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
device and array organization figure 9: device organization for single-die package (tsop) async sync ce# ce# cle cle ale ale we# clk re# w/r# dq[7:0] dq[7:0] n/a dqs wp# wp# lun 1 target 1 package r/b# note: 1. tsop devices do not support the synchronous interface. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand device and array organization pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 10: device organization for two-die package (tsop) ce# cle ale clk w/r# dq[7:0] dqs wp# lun 1 target 1 package r/b# ce2# cle ale clk w/r# dq[7:0] dqs wp# ce# cle ale we# re# dq[7:0] n/a wp# ce2# cle ale we# re# dq[7:0] n/a wp# lun 1 target 2 r/b2# async sync note: 1. tsop devices do not support the synchronous interface. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand device and array organization pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 11: device organization for two-die package (bga/lga) ce# cle-1 ale-1 clk-1 w/r#-1 dq[7:0]-1 dqs-1 wp#-1 lun 1 target 1 package r/b# ce2# cle-2 ale-2 clk-2 w/r#-2 dq[7:0]-2 dqs-2 wp#-2 ce# cle-1 ale-1 we#-1 re#-1 dq[7:0]-1 n/a wp#-1 ce2# cle-2 ale-2 we#-2 re#-2 dq[7:0]-2 n/a wp#-2 lun 1 target 2 r/b2# async sync note: 1. lga devices do not support the synchronous interface. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand device and array organization pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 12: device organization for four-die package with four ce# and two r/b# (lga) ce# cle-1 ale-1 clk-1 w/r#-1 dq[7:0]-1 dqs-1 wp#-1 sync ce# cle-1 ale-1 we#-1 re#-1 dq[7:0]-1 n/a wp#-1 async lun 1 target 1 package r/b# ce2# cle-2 ale-2 clk-2 w/r#-2 dq[7:0]-2 dqs-2 wp#-2 ce2# cle-2 ale-2 we#-2 re#-2 dq[7:0]-2 n/a wp#-2 lun 1 target 2 r/b2# ce3# cle-1 ale-1 clk-1 w/r#-1 dq[7:0]-1 dqs-1 wp#-1 ce3# cle-1 ale-1 we#-1 re#-1 dq[7:0]-1 n/a wp#-1 lun 1 target 3 r/b# ce4# cle-2 ale-2 clk-2 w/r#-2 dq[7:0]-2 dqs-2 wp#-2 ce4# cle-2 ale-2 we#-2 re#-2 dq[7:0]-2 n/a wp#-2 lun 1 target 4 r/b2# note: 1. lga devices do not support the synchronous interface. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand device and array organization pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 13: array organization per logical unit (lun) cache registers data registers 2048 blocks per plane 4096 blocks per lun 1 block 1 block plane 0 (0, 2, 4, ..., 4094) plane 1 (1, 3, 5, ..., 4095) 224 4096 224 4320 bytes 4320 bytes 224 224 4096 4096 4096 1 block 1 page = (4k + 224 bytes) 1 block = (4k + 224) bytes x 256 pages = (1024k + 56k) bytes 1 plane = (1024k + 56k) bytes x 2048 blocks = 17,280mb 1 lun = 17,280mb x 2 planes = 34,560mb dq0 dq7 logical unit (lun) table 2: array addressing for logical unit (lun) cycle dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 2 second low low low ca12 3 ca11 ca10 ca9 ca8 third pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 4 fifth low low low la0 5 ba19 ba18 ba17 ba16 notes: 1. cax = column address, pax = page address, bax = block address, lax = lun address; the page address, block address, and lun address are collectively called the row address. 2. when using the synchronous interface, ca0 is forced to 0 internally; one data cycle al- ways returns one even byte and one odd byte. 3. column addresses 4320 (10e0h) through 8191 (1fffh) are invalid, out of bounds, do not exist in the device, and cannot be addressed. 4. ba[8] is the plane-select bit: plane 0: ba[8] = 0 plane 1: ba[8] = 1 5. la0 is the lun-select bit. it is present only when two luns are shared on the target; otherwise, it should be held low. lun 0: la0 = 0 lun 1: la0 = 1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand device and array organization pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
bus operation C asynchronous interface the asynchronous interface is active when the nand flash device powers on. the i/o bus, dq[7:0], is multiplexed sharing data i/o, addresses, and commands. the dqs sig- nal, if present, is tri-stated when the asynchronous interface is active. asynchronous interface bus modes are summarized below. table 3: asynchronous interface mode selection mode ce# cle ale we# re# dqs dqx wp# notes standby h x x x x x x 0v/v ccq 2 2 bus idle l x x h h x x x command input l h l h x input h address input l l h h x input h data input l l l h x input h data output l l l h x output x write protect x x x x x x x l notes: 1. dqs is tri-stated when the asynchronous interface is active. 2. wp# should be biased to cmos low or high for standby. 3. mode selection settings for this table: h = logic level high; l = logic level low; x = v ih or v il . asynchronous enable/standby a chip enable (ce#) signal is used to enable or disable a target. when ce# is driven low, all of the signals for that target are enabled. with ce# low, the target can accept commands, addresses, and data i/o. there may be more than one target in a nand flash package. each target is controlled by its own chip enable; the first target (target 0) is controlled by ce#; the second target (if present) is controlled by ce2#, etc. a target is disabled when ce# is driven high, even when the target is busy. when disa- bled, all of the target's signals are disabled except ce#, wp#, and r/b#. this functionali- ty is also known as ce# "don't care". while the target is disabled, other devices can utilize the disabled nand signals that are shared with the nand flash. a target enters low-power standby when it is disabled and is not busy. if the target is busy when it is disabled, the target enters standby after all of the die (luns) complete their operations. standby helps reduce power consumption. asynchronous bus idle a target's bus is idle when ce# is low, we# is high, and re# is high. during bus idle, all of the signals are enabled except dqs, which is not used when the asynchronous interface is active. no commands, addresses, and data are latched into the target; no data is output. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C asynchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
asynchronous commands an asynchronous command is written from dq[7:0] to the command register on the rising edge of we# when ce# is low, ale is low, cle is high, and re# is high. commands are typically ignored by die (luns) that are busy (rdy = 0); however, some commands, including read status (70h) and read status enhanced (78h), are accepted by die (luns) even when they are busy. figure 14: asynchronous command latch cycle we# ce# ale cle dqx command t wp t ch t cs t alh t dh t ds t als t clh t cls dont care micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C asynchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
asynchronous addresses an asynchronous address is written from dq[7:0] to the address register on the rising edge of we# when ce# is low, ale is high, cle is low, and re# is high. bits that are not part of the address space must be low (see device and array organiza- tion). the number of cycles required for each command varies. refer to the command descriptions to determine addressing requirements (see command definitions). addresses are typically ignored by die (luns) that are busy (rdy = 0); however, some addresses are accepted by die (luns) even when they are busy; for example, address cycles that follow the read status enhanced (78h) command. figure 15: asynchronous address latch cycle we# ce# ale cle dqx col add 1 t wp t wh t cs t dh t ds t als t alh t cls col add 2 row add 1 row add 2 row add 3 dont care undefined t wc micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C asynchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
asynchronous data input data is written from dq[7:0] to the cache register of the selected die (lun) on the rising edge of we# when ce# is low, ale is low, cle is low, and re# is high. data input is ignored by die (luns) that are not selected or are busy (rdy = 0). figure 16: asynchronous data input cycles we# ce# ale cle dqx t wp t wp t wp t wh t als t dh t ds t dh t ds t dh t ds t clh t ch d in m+1 d in n dont care t wc d in m micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C asynchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
asynchronous data output data can be output from a die (lun) if it is in a ready state. data output is supported following a read operation from the nand flash array. data is output from the cache register of the selected die (lun) to dq[7:0] on the falling edge of re# when ce# is low, ale is low, cle is low, and we# is high. if the host controller is using a t rc of 30ns or greater, the host can latch the data on the rising edge of re# (see figure 17 for proper timing). if the host controller is using a t rc of less than 30ns, the host can latch the data on the next falling edge of re# (see fig- ure 18 (page 28) for extended data output (edo) timing). using the read status enhanced (78h) command prevents data contention follow- ing an interleaved die (multi-lun) operation. after issuing the read status en- hanced (78h) command, to enable data output, issue the read mode (00h) command. data output requests are typically ignored by a die (lun) that is busy (rdy = 0); howev- er, it is possible to output data from the status register even when a die (lun) is busy by first issuing the read status (70h) or read status enhanced (78h) command. figure 17: asynchronous data output cycles ce# re# dqx t reh t rp t rr t rc t cea t rea t rea t rea dont care t rhz t chz t rhz t rhoh rdy t coh dout dout dout micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C asynchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 18: asynchronous data output cycles (edo mode) dout dout dout ce# re# dqx rdy t rr t cea t rea t rp t reh t rc t rloh t rea t rhoh t rhz t coh t chz dont care write protect the write protect# (wp#) signal enables or disables program and erase operations to a target. when wp# is low, program and erase operations are disabled. when wp# is high, program and erase operations are enabled. it is recommended that the host drive wp# low during power-on until vcc and vccq are stable to prevent inadvertent program and erase operations (see device initiali- zation (page 41) for additional details). wp# must be transitioned only when the target is not busy and prior to beginning a command sequence. after a command sequence is complete and the target is ready, wp# can be transitioned. after wp# is transitioned, the host must wait t ww before issu- ing a new command. the wp# signal is always an active input, even when ce# is high. this signal should not be multiplexed with other signals. ready/busy# the ready/busy# (r/b#) signal provides a hardware method of indicating whether a tar- get is ready or busy. a target is busy when one or more of its die (luns) are busy (rdy = 0). a target is ready when all of its die (luns) are ready (rdy = 1). because each die (lun) contains a status register, it is possible to determine the independent status of each die (lun) by polling its status register instead of using the r/b# signal (see sta- tus operations (page 65) for details regarding die (lun) status). this signal requires a pull-up resistor, rp, for proper operation. r/b# is high when the target is ready, and transitions low when the target is busy. the signal's open-drain micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C asynchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
driver enables multiple r/b# outputs to be or-tied. typically, r/b# is connected to an interrupt pin on the system controller (see figure 19 (page 29)). the combination of rp and capacitive loading of the r/b# circuit determines the rise time of the r/b# signal. the actual value used for rp depends on the system timing re- quirements. large values of rp cause r/b# to be delayed significantly. between the 10- to 90-percent points on the r/b# waveform, the rise time is approximately two time constants (tc). tc = r c where r = rp (resistance of pull-up resistor), and c = total capacitive load. the fall time of the r/b# signal is determined mainly by the output impedance of the r/b# signal and the total load capacitance. approximate rp values using a circuit load of 100pf are provided in figure 24 (page 32). the minimum value for rp is determined by the output drive capability of the r/b# signal, the output voltage swing, and vccq. rp = vcc (max) - vol (max) iol + il where il is the sum of the input currents of all devices tied to the r/b# pin. figure 19: read/busy# open drain rp vcc vccq r/b# open drain output iol vss device to controller micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C asynchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 20: t fall and t rise (v ccq = 2.7-3.6v) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 C1 0 2 4 0 2 4 6 t fall t rise vccq 3.3v tc v notes: 1. t fall is v oh(dc) to v ol(ac) and t rise is v ol(dc) to v oh(ac) . 2. t rise dependent on external capacitance and resistive loading and output transistor im- pedance. 3. t rise primarily dependent on external pull-up resistor and external capacitive loading. 4. t fall = 10ns at 3.3v 5. see tc values in figure 24 (page 32) for approximate rp value and tc. figure 21: t fall and t rise (v ccq = 1.7-1.95v) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 2 4 6 t fall t rise vccq 1.8v tc v notes: 1. t fall is v oh(dc) to v ol(ac) and t rise is v ol(dc) to v oh(ac) . 2. t rise is primarily dependent on external pull-up resistor and external capacitive loading. 3. t fall 7ns at 1.8v. 4. see tc values in figure 24 (page 32) for tc and approximate rp value. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C asynchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 22: iol vs rp (v ccq = 2.7-3.6v) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2000 400 0 6000 8000 10,000 12,000 iol at vccq (max) rp ( ) i (ma) figure 23: iol vs rp (v ccq = 1.7-1.95v) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2000 4000 6000 8000 10,000 12,000 rp ( ) i (ma) iol at vccq (max) micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C asynchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 24: tc vs rp 1200 1000 800 600 400 200 0 0 2000 4000 6000 8000 10,000 12,000 iol at vccq (max) rc = tc c = 100pf rp ( ) t(ns) micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C asynchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
bus operation C synchronous interface these nand flash devices have two interfacesa synchronous interface for fast data i/o transfer and an asynchronous interface that is backward compatible with existing nand flash devices. the nand flash command protocol for both the asynchronous and synchronous inter- faces is identical. however, there are some differences betweeen the asynchronous and synchronous interfaces when issuing command, address, and data i/o cycles using the nand flash signals. when the synchronous interface is activated on a target (see activating interfaces (page 42)), the target is capable of high-speed ddr data transfers. existing signals are redefined for high-speed ddr i/o. the we# signal becomes clk. dqs is enabled. the re# signal becomes w/r#. clk provides a clock reference to the nand flash device. dqs is a bidirectional data strobe. during data output, dqs is driven by the nand flash device. during data input, dqs is controlled by the host controller while input- ting data on dq[7:0]. the direction of dqs and dq[7:0] is controlled by the w/r# signal. when the w/r# sig- nal is latched high, the controller is driving the dq bus and dqs. when the w/r# is latched low, the nand flash is driving the dq bus and dqs. the synchronous interface bus modes are summarized below. table 4: synchronous interface mode selection mode ce# cle ale clk w/r# dqs dq[7:0] wp# notes standby h x x x x x x 0v/v ccq 1, 2 bus idle l l l h x x x bus driv- ing l l l l output output x command input l h l h x input h 3 address input l l h h x input h 3 data input l h h h input h 4 data out- put l h h l see note 5 output x 5 write pro- tect x x x x x x x l undefined l l h l output output x undefined l h l l output output x notes: 1. clk can be stopped when the target is disabled, even when r/b# is low. 2. wp# should be biased to cmos low or high for standby. 3. commands and addresses are latched on the rising edge of clk. 4. during data input to the device, dqs is the clock that latches the data in the cache register. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C synchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
5. during data output from the nand flash device, dqs is an output generated from clk after t dqsck delay. 6. mode selection settings for this table: h = logic level high; l = logic level low; x = v ih or v il . synchronous enable/standby in addition to the description in the section asynchronous enable/standby (page 23), the following requirements also apply when the synchronous interface is active. before enabling a target, clk must be running and ale and cle must be low. when ce# is driven low, all of the signals for the selected target are enabled. the target is not enabled until t cs completes; the target's bus is then idle. prior to disabling a target, the target's bus must be idle. a target is disabled when ce# is driven high, even when it is busy. all of the target's signals are disabled except ce#, wp#, and r/b#. after the target is disabled, clk can be stopped. a target enters low-power standby when it is disabled and is not busy. if the target is busy when it is disabled, the target enters standby after all of the die (luns) complete their operations. synchronous bus idle/driving a target's bus is idle or driving when clk is running, ce# is low, ale is low, and cle is low. the bus is idle when w/r# transitions high and is latched by clk. during the bus idle mode, all signals are enabled; dqs and dq[7:0] are inputs. no commands, addresses, or data are latched into the target; no data is output. when entering the bus idle mode, the host must wait a minimum of t cad before changing the bus mode. in the bus idle mode, the only valid bus modes supported are: bus driving, command, address, and ddr data input. the bus is driving when w/r# transitions low and is latched by clk. during the bus driving mode, all signals are enabled; dqs is low and dq[7:0] is driven low or high, but no valid data is output. following the bus driving mode, the only valid bus modes supported are bus idle and ddr data output. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C synchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 25: synchronous bus idle/driving behavior ce# cle ale clk w/r# dqs dq[7:0] undefined (driven by nand) t cals t dqsd t dqshz t cals bus idle bus idle bus driving note: 1. only the selected die (lun) drives dqs and dq[7:0]. during an interleaved die (multi- lun) operation, the host must use the read status enhanced (78h) to prevent data output contention. synchronous commands a command is written from dq[7:0] to the command register on the rising edge of clk when ce# is low, ale is low, cle is high, and w/r# is high. after a command is latchedand prior to issuing the next command, address, or data i/othe bus must go to bus idle mode on the next rising edge of clk, except when the clock period, t ck, is greater than t cad. commands are typically ignored by die (luns) that are busy (rdy = 0); however, some commands, such as read status (70h) and read status enhanced (78h), are ac- cepted by die (luns), even when they are busy. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C synchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 26: synchronous command cycle clk ale cle dqs dq[7:0] t ckl t calh t cah t cas t cals t calh t cals dont care t ckh t calh t cals t cals ce# t ch t cs t cad starts here 1 t cad w/r# t ck t calh t cals t dqshz command undefined note: 1. when ce# remains low, t cad begins at the rising edge of the clock from which the command cycle is latched for subsequent command, address, data input, or data output cycle(s). synchronous addresses a synchronous address is written from dq[7:0] to the address register on the rising edge of clk when ce# is low, ale is high, cle is low, and w/r# is high. after an address is latchedand prior to issuing the next command, address, or data i/o the bus must go to bus idle mode on the next rising edge of clk, except when the clock period, t ck, is greater than t cad. bits not part of the address space must be low (see device and array organization). the number of address cycles required for each command varies. refer to the com- mand descriptions to determine addressing requirements. addresses are typically ignored by die (luns) that are busy (rdy = 0); however, some addresses such as address cycles that follow the read status enhanced (78h) com- mand, are accepted by die (luns), even when they are busy. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C synchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 27: synchronous address cycle clk ale cle dqs dq[7:0] t ckl t calh t cals t calh t cals dont care undefined t ckh t cals t calh t cals t calh t cals ce# t ch t cs t cad w/r# t ck t dqshz t cah t cas address t cad starts here 1 note: 1. when ce# remains low, t cad begins at the rising edge of the clock from which the command cycle is latched for subsequent command, address, data input, or data output cycle(s). synchronous ddr data input to enter the ddr data input mode, the following conditions must be met: ? clk is running ? ce# is low ? w/r# is high ? t cad is met ? dqs is low ? ale and cle are high on the rising edge of clk upon entering the ddr data input mode after t dqss, data is written from dq[7:0] to the cache register on each and every rising and falling edge of dqs (center-aligned) when clk is running and the dqs to clk skew meets t dsh and t dss, ce# is low, w/r# is high, and ale and cle are high on the rising edge of clk. to exit ddr data input mode, the following conditions must be met: ? clk is running and the dqs to clk skew meets t dsh and t dss ? ce# is low ? w/r# is high micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C synchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
? ale and cle are latched low on the rising edge of clk ? the final two data bytes of the data input sequence are written to dq[7:0] to the cache register on the rising and falling edges of dqs after the last cycle in the data input sequence in which ale and cle are latched high. ? dqs is held low for t wpst (after the final falling edge of dqs) following t wpst, the bus enters bus idle mode and t cad begins on the next rising edge of clk. after t cad starts, the host can disable the target if desired. data input is ignored by die (luns) that are not selected or are busy. figure 28: synchronous ddr data input cycles clk ale cle dq[7:0] dqs t ckl t calh t dh t ds t dqss t cals t calh t cals dont care t ckh t calh t cals t cals t calh t cals t cals ce# t ch t cs t cad w/r# t ck t dqsl t wpre t dqsl t dqsh t dqsh t dqsh t wpst d n-1 d 2 t dsh t dsh t dss t dsh t dss t dsh t dss t dh t ds d 3 d n-2 d n d 0 d 1 t cad starts here 1 notes: 1. when ce# remains low, t cad begins at the first rising edge of the clock after t wpst completes. 2. t dsh (min) generally occurs during t dqss (min). 3. t dss (min) generally occurs during t dqss (max). synchronous ddr data output data can be output from a die (lun) if it is ready. data output is supported following a read operation from the nand flash array. to enter the ddr data output mode, the following conditions must be met: ? clk is running ? ce# is low ? the host has released the dq[7:0] bus and dqs ? w/r# is latched low on the rising edge of clk to enable the selected die (lun) to take ownership of the dq[7:0] bus and dqs within t wrck ? t cad is met ? ale and cle are high on the rising edge of clk micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C synchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
upon entering the ddr data output mode, dqs will toggle high and low with a delay of t dqsck from the respective rising and falling edges of clk. dq[7:0] will output data edge-aligned to the rising and falling edges of dqs, with the first transition delayed by no more than t ac. ddr data output mode continues as long as clk is running, ce# is low, w/r# is low, and ale and cle are high on the rising edge of clk. to exit ddr data output mode, the following conditions must be met: ? clk is running ? ce# is low ? w/r# is low ? ale and cle are latched low on the rising edge of clk the final two data bytes are output on dq[7:0] on the final rising and falling edges of dqs. the final rising and falling edges of dqs occur t dqsck after the last cycle in the data output sequence in which ale and cle are latched high. after t ckwr, the bus enters bus idle mode and t cad begins on the next rising edge of clk. once t cad starts the host can disable the target if desired. data output requests are typically ignored by a die (lun) that is busy (rdy = 0); howev- er, it is possible to output data from the status register even when a die (lun) is busy by issuing the read status (70h) or read status enhanced (78h) command. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C synchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 29: synchronous ddr data output cycles clk ale cle dq[7:0] dqs t ckl t calh t cals t calh t cals dont care t ckh t calh t cals t cals t calh t cals t cals t cals t cals ce# t ch t cs t cad t dqsd t wrck t dqsck t ac w/r# t dqsck t dqsck t ckwr t dqsck t dqsck t dqsck t dqshz t dqsq t qh t dqsq t ck t hp t hp t hp t hp t hp t hp data transitioning t dvw t qh t dvw t qh t dvw t qh t dvw t dvw t cad starts here 1 undefined (driven by nand) d 0 d 1 d 2 d n-1 d n-2 d n t dqsq t dqsq notes: 1. when ce# remains low, t cad begins at the rising edge of the clock after t ckwr for subsequent command or data output cycle(s). 2. see figure 26 (page 36) for details of w/r# behavior. 3. t ac is the dq output window relative to clk and is the long-term component of dq skew. 4. for w/r# transitioning high, dq[7:0] and dqs go to tri-state. 5. for w/r# transitioning low, dq[7:0] drives current state and dqs goes low. 6. after final data output, dq[7:0] is driven until w/r# goes high, but is not valid. write protect see write protect (page 28). ready/busy# see ready/busy# (page 28). micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand bus operation C synchronous interface pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
device initialization some nand flash devices do not support v ccq . for these devices all references to v ccq are replaced with v cc . micron nand flash devices are designed to prevent data corruption during power tran- sitions. v cc is internally monitored. (the wp# signal supports additional hardware protection during power transitions.) when ramping v cc and v ccq , use the following procedure to initialize the device: 1. ramp v cc . 2. ramp v ccq . v ccq must not exceed v cc . 3. the host must wait for r/b# to be valid and high before issuing reset (ffh) to any target (see figure 30). the r/b# signal becomes valid when 50s has elapsed since the beginning the v cc ramp, and 10s has elapsed since v ccq reaches v ccq (min) and v cc reaches v cc (min). 4. if not monitoring r/b#, the host must wait at least 100s after v ccq reaches v ccq (min) and v cc reaches v cc (min). if monitoring r/b#, the host must wait until r/b# is high. 5. the asynchronous interface is active by default for each target. each lun draws less than an average of 10ma (i st ) measured over intervals of 1ms until the reset (ffh) command is issued. 6. the reset (ffh) command must be the first command issued to all targets (ce#s) after the nand flash device is powered on. each target will be busy for t por after a reset command is issued. the reset busy time can be monitored by polling r/b# or issuing the read status (70h) command to poll the status register. 7. the device is now initialized and ready for normal operation. at power-down, v ccq must go low, either before, or simultaneously with, v cc going low. figure 30: r/b# power-on behavior reset (ffh) is issued 50s (min) 100s (max) invalid 10s (max) > 0s vcc ramp starts vccq vcc r/b# vccq = vccq (min) vcc = vcc (min) note: 1. disregard v ccq for devices that use only v cc . micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand device initialization pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
activating interfaces after performing the steps under device initialization (page 41), the asynchronous inter- face is active for all targets on the device. each target's interface is independent of other targets, so the host is responsible for changing the interface for each target. if the host and nand flash device, through error, are no longer using the same inter- face, then steps under activating the asynchronous interface are performed to re- synchronize the interfaces. activating the asynchronous interface to activate the asynchronous nand interface, once the synchronous interface is active, the following steps are repeated for each target: 1. the host pulls ce# high, disables its input to clk, and enables its asynchronous interface. 2. the host pulls ce# low and issues the reset (ffh) command, using an asynchro- nous command cycle. 3. r/b# goes low for t rst. 4. after t itc, and during t rst, the device enters the asynchronous nand interface. read status (70h) and read status enhanced (78h) are the only com- mands that can be issued. 5. after t rst, r/b# goes high. timing mode feature address (01h), subfeature param- eter p1 is set to 00h, indicating that the asynchronous nand interface is active and that the device is set to timing mode 0. for further details, see reset operations. activating the synchronous interface to activate the synchronous nand flash interface, the following steps are repeated for each target: 1. issue the set features (efh) command. 2. write address 01h, which selects the timing mode. 3. write p1 with 1xh, where "x" is the timing mode used in the synchronous inter- face (see configuration operations). 4. write p2Cp4 as 00h-00h-00h. 5. r/b# goes low for t itc. the host should pull ce# high. during t itc, the host should not issue any type of command, including status commands, to the nand flash device. 6. after t itc, r/b# goes high and the synchronous interface is enabled. before pull- ing ce# low, the host should enable the clock. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand activating interfaces pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 31: activating the synchronous interface cycle type dq[7:0] r/b# cmd addr d in d in d in d in efh 01h tm p2 p3 p4 t adl t wb t cad ce# may transition high ce# may transition low 100ns t itc a c b note: 1. tm = timing mode. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand activating interfaces pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
command definitions table 5: command set command command cycle #1 number of valid address cycles data input cycles command cycle #2 valid while selected lun is busy 1 valid while other luns are busy 2 notes reset operations reset ffh 0 C C yes yes synchronous reset fch 0 C C yes yes reset lun fah 3 C C yes yes identification operations read id 90h 1 C C 3 read parameter page ech 1 C C read unique id edh 1 C C configuration operations get features eeh 1 C C 3 set features efh 1 4 C 4 status operations read status 70h 0 C C yes read status enhanced 78h 3 C C yes yes column address operations change read column 05h 2 C e0h yes change read column enhanced 06h 5 C e0h yes change write column 85h 2 optional C yes change row address 85h 5 optional C yes 5 read operations read mode 00h 0 C C yes read page 00h 5 C 30h yes 6 read page multi- plane 00h 5 C 32h yes read page cache sequential 31h 0 C C yes 7 read page cache random 00h 5 C 31h yes 6,7 read page cache last 3fh 0 C C yes 7 program operations program page 80h 5 yes 10h yes program page multi-plane 80h 5 yes 11h yes program page cache 80h 5 yes 15h yes 8 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand command definitions pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 5: command set (continued) command command cycle #1 number of valid address cycles data input cycles command cycle #2 valid while selected lun is busy 1 valid while other luns are busy 2 notes erase operations erase block 60h 3 C d0h yes erase block multi-plane 60h 3 C d1h yes copyback operations copyback read 00h 5 C 35h yes 6 copyback program 85h 5 optional 10h yes copyback program multi-plane 85h 5 optional 11h yes notes: 1. busy means rdy = 0. 2. these commands can be used for interleaved die (multi-lun) operations (see interleaved die (multi-lun) operations (page 100)). 3. the read id (90h) and get features (eeh) output identical data on rising and falling dqs edges. 4. the set features (efh) command requires data transition prior to the rising edge of clk, with identical data for the rising and falling edges. 5. command cycle #2 of 11h is conditional. see change row address (85h) (page 71) for more details. 6. this command can be preceded by up to one read page multi-plane (00h-32h) com- mand to accommodate a maximum simultaneous two-plane array operation. 7. issuing a read page cache-series (31h, 00h-31h, 00h-32h, 3fh) command when the ar- ray is busy (rdy = 1, ardy = 0) is supported if the previous command was a read page (00h-30h) or read page cache-series command; otherwise, it is prohibited. 8. issuing a program page cache (80h-15h) command when the array is busy (rdy = 1, ardy = 0) is supported if the previous command was a program page cache (80h-15h) command; otherwise, it is prohibited. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand command definitions pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
reset operations reset (ffh) the reset (ffh) command is used to put a target into a known condition and to abort command sequences in progress. this command is accepted by all die (luns), even when they are busy. when ffh is written to the command register, the target goes busy for t rst. during t rst, the selected target (ce#) discontinues all array operations on all die (luns). all pending single- and multi-plane operations are cancelled. if this command is issued while a program or erase operation is occurring on one or more die (luns), the data may be partially programmed or erased and is invalid. the command register is cleared and ready for the next command. the data register and cache register contents are invalid. reset must be issued as the first command to each target following power-up (see de- vice initialization (page 41)). use of the read status enhanced (78h) command is prohibited during the power-on reset. to determine when the target is ready, use read status (70h). if the reset (ffh) command is issued when the synchronous interface is enabled, the target's interface is changed to the asynchronous interface and the timing mode is set to 0. the reset (ffh) command can be issued asynchronously when the synchronous interface is active, meaning that clk does not need to be continuously running when ce# is transitioned low and ffh is latched on the rising edge of clk. after this com- mand is latched, the host should not issue any commands during t itc. after t itc, and during or after t rst, the host can poll each lun's status register. if the reset (ffh) command is issued when the asynchronous interface is active, the target's asynchronous timing mode remains unchanged. during or after t rst, the host can poll each lun's status register. figure 32: reset (ffh) operation cycle type dq[7:0] r/b# t rst t wb ffh command micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand reset operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
synchronous reset (fch) when the synchronous interface is active, the synchronous reset (fch) command is used to put a target into a known condition and to abort command sequences in pro- gress. this command is accepted by all die (luns), even when they are busy. when fch is written to the command register, the target goes busy for t rst. during t rst, the selected target (ce#) discontinues all array operations on all die (luns). all pending single- and multi-plane operations are cancelled. if this command is issued while a program or erase operation is occurring on one or more die (luns), the data may be partially programmed or erased and is invalid. the command register is cleared and ready for the next command. the data register and cache register contents are inva- lid and the synchronous interface remains active. during or after t rst, the host can poll each lun's status register. synchronous reset is only accepted while the synchronous interface is active. its use is prohibited when the asynchronous interface is active. figure 33: synchronous reset (fch) operation cycle type dq[7:0] r/b# t rst t wb fch command micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand reset operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
reset lun (fah) the reset lun (fah) command is used to put a particular lun on a target into a known condition and to abort command sequences in progress. this command is ac- cepted by only the lun addressed by the reset lun (fah) command, even when that lun is busy. when fah is written to the command register, the addressed lun goes busy for t rst. during t rst, the selected lun discontinues all array operations. all pending single- and multi-plane operations are canceled. if this command is issued while a program or erase operation is occurring on the addressed lun, the data may be partially pro- grammed or erased and is invalid. the command register is cleared and ready for the next command. the data register and cache register contents are invalid. if the reset lun (fah) command is issued when the synchronous interface is enabled, the targets's interface remains in synchronous mode. if the reset lun (fah) command is issued when the asynchronous interface is ena- bled, the target's interface remains in asynchronous mode. during or after t rst, the host can poll each lun's status register. the reset lun (fah) command is prohibited when not in the default array operation mode. the reset lun (fah) command can only be issued to a target (ce#) after the reset (ffh) command has been issued as the first command to a target following power-up. figure 34: reset lun (fah) operation cycle type dq[7:0] r/b# t rst t wb fah command r1 address address address r2 r3 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand reset operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
identification operations read id (90h) the read id (90h) command is used to read identifier codes programmed into the tar- get. this command is accepted by the target only when all die (luns) on the target are idle. writing 90h to the command register puts the target in read id mode. the target stays in this mode until another valid command is issued. when the 90h command is followed by a 00h address cycle, the target returns a 5-byte identifier code that includes the manufacturer id, device configuration, and part-specif- ic information. when the 90h command is followed by a 20h address cycle, the target returns the 4-byte onfi identifier code. after the 90h and address cycle are written to the target, the host enables data output mode to read the identifier information. when the asynchronous interface is active, one data byte is output per re# toggle. when the synchronous interface is active, one data byte is output per rising edge of dqs when ale and cle are high; the data byte on the falling edge of dqs is identical to the data byte output on the previous rising edge of dqs. figure 35: read id (90h) with 00h address operation cycle type dq[7:0] t whr command 90h 00h byte 0 byte 1 byte 2 byte 3 address dout dout dout dout dout dout dout dout byte 4 byte 5 byte 6 byte 7 note: 1. see the read id parameter tables for byte definitions. figure 36: read id (90h) with 20h address operation cycle type dq[7:0] t whr command 90h 20h 4fh 4eh 46h 49h address dout dout dout dout note: 1. see the read id parameter tables for byte definitions. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand identification operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
read id parameter tables table 6: read id parameters for address 00h device byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 mt29f32g08cbaca 2ch 68h 04h 4ah a9h 00h 00h 00h mt29f64g08ceaca 2ch 68h 04h 4ah a9h 00h 00h 00h mt29f64g08ceccb 2ch 68h 04h 4ah a9h 00h 00h 00h mt29f64g08cfaca 2ch 68h 04h 4ah a9h 00h 00h 00h MT29F128G08CXACA 2ch 68h 04h 4ah a9h 00h 00h 00h note: 1. h = hexadecimal. table 7: read id parameters for address 20h device byte 0 byte 1 byte 2 byte 3 byte 4 all 4fh 4eh 46h 49h xxh notes: 1. h = hexadecimal. 2. xxh = undefined. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read id parameter tables pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
configuration operations the set features (efh) and get features (eeh) commands are used to modify the target's default power-on behavior. these commands use a one-byte feature address to determine which subfeature parameters will be read or modified. each feature address (in the 00h to ffh range) is defined in table 8. the set features (efh) command writes subfeature parameters (p1-p4) to the specified feature address. the get fea- tures command reads the subfeature parameters (p1-p4) at the specified feature address. unless otherwise specifed, the values of the feature addresses do not change when re- set (ffh, fch) is issued by the host. table 8: feature address definitions feature address definition 00h reserved 01h timing mode 02hC0fh reserved 10h programmable output drive strength 11hC7fh reserved 80h programmable output drive strength 81h programmable rb# pull-down strength 82hC8fh reserved 90h array operation mode 91hCffh reserved set features (efh) the set features (efh) command writes the subfeature parameters (p1-p4) to the specified feature address to enable or disable target-specific features. this command is accepted by the target only when all die (luns) on the target are idle. writing efh to the command register puts the target in the set features mode. the tar- get stays in this mode until another command is issued. the efh command is followed by a valid feature address as specified in table 8. the host waits for t adl before the subfeature parameters are input. when the asynchro- nous interface is active, one subfeature parameter is latched per rising edge of we#. when the synchronous interface is active, one subfeature parameter is latched per ris- ing edge of dqs. the data on the falling edge of dqs should be identical to the subfeature parameter input on the previous rising edge of dqs. the device is not re- quired to wait for the repeated data byte before beginning internal actions. after all four subfeature parameters are input, the target goes busy for t feat. the read status (70h) command can be used to monitor for command completion. feature address 01h (timing mode) operation is unique. if set features is used to modify the interface type, the target will be busy for t itc. see activating interfaces (page 42) for details. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand configuration operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 37: set features (efh) operation cycle type dq[7:0] r/b# t adl command address efh fa din din din din p1 p2 p3 p4 t wb t feat get features (eeh) the get features (eeh) command reads the subfeature parameters (p1-p4) from the specified feature address. this command is accepted by the target only when all die (luns) on the target are idle. writing eeh to the command register puts the target in get features mode. the target stays in this mode until another valid command is issued. when the eeh command is followed by a feature address, the target goes busy for t feat. if the read status (70h) command is used to monitor for command comple- tion, the read mode (00h) command must be used to re-enable data output mode. during and prior to data output, use of the read status enhanced (78h) command is prohibited. after t feat completes, the host enables data output mode to read the subfeature param- eters. when the asynchronous interface is active, one data byte is output per re# toggle. when the synchronous interface is active, one subfeature parameter is output per dqs toggle on rising or falling edge of dqs. figure 38: get features (eeh) operation cycle type dq[7:0] r/b# t wb t feat t rr command address d out eeh fa p1 p2 d out d out p3 p4 d out micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand configuration operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 9: feature address 01h: timing mode subfeature pa- rameter options dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 value notes p1 timing mode mode 0 (default) 0 0 0 0 x0h 1, 2 mode 1 0 0 0 1 x1h mode 2 0 0 1 0 x2h mode 3 0 0 1 1 x3h mode 4 0 1 0 0 x4h mode 5 0 1 0 1 x5h data interface asynchronous (de- fault) 0 0 0xh 1 synchronous ddr 0 1 1xh reserved 1 x 2xh program clear program com- mand clears all cache registers on a target (default) 0 0b program com- mand clears only addressed lun cache register on a target 1 1b reserved 0 0b p2 reserved 0 0 0 0 0 0 0 0 00h p3 reserved 0 0 0 0 0 0 0 0 00h p4 reserved 0 0 0 0 0 0 0 0 00h notes: 1. asynchronous timing mode 0 is the default, power-on value. 2. if the synchronous interface is active, a reset (ffh) command will change the timing mode and data interface bits of feature address 01h to their default values. if the asyn- chronous interface is active, a reset (ffh) command will not change the values of the timing mode or data interface bits to their default valued. table 10: feature addresses 10h and 80h: programmable output drive strength subfeature pa- rameter options dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 value notes p1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand configuration operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 10: feature addresses 10h and 80h: programmable output drive strength (continued) subfeature pa- rameter options dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 value notes output drive strength overdrive 2 0 0 00h 1 overdrive 1 0 1 01h nominal (de- fault) 1 0 02h underdrive 1 1 03h reserved 0 0 0 0 0 0 00h p2 reserved 0 0 0 0 0 0 0 0 00h p3 reserved 0 0 0 0 0 0 0 0 00h p4 reserved 0 0 0 0 0 0 0 0 00h note: 1. see output drive impedance (page 102) for details. table 11: feature addresses 81h: programmable r/b# pull-down strength subfeature pa- rameter options dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 value notes p1 r/b# pull-down strength full (default) 0 0 00h 1 three-quarter 0 1 01h one-half 1 0 02h one-quarter 1 1 03h reserved 0 0 0 0 0 0 00h p2 reserved 0 0 0 0 0 0 0 0 00h p3 reserved 0 0 0 0 0 0 0 0 00h p4 reserved 0 0 0 0 0 0 0 0 00h note: 1. this feature address is used to change the default r/b# pull-down strength. its strength should be selected based on the expected loading of r/b#. full strength is the default, power-on value. table 12: feature addresses 90h: array operation mode subfeature pa- rameter options dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 value notes p1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand configuration operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 12: feature addresses 90h: array operation mode (continued) subfeature pa- rameter options dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 value notes array operation mode normal (de- fault) 0 00h otp block 1 01h 1 reserved 0 0 0 0 0 0 0 00h p2 reserved 0 0 0 0 0 0 0 0 00h p3 reserved 0 0 0 0 0 0 0 0 00h p4 reserved 0 0 0 0 0 0 0 0 00h notes: 1. see one-time programmable (otp) operations for details. 2. a reset (ffh) command will cause the bits of the array operation mode to change to their default values. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand configuration operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
read parameter page (ech) the read parameter page (ech) command is used to read the onfi parameter page programmed into the target. this command is accepted by the target only when all die (luns) on the target are idle. writing ech to the command register puts the target in read parameter page mode. the target stays in this mode until another valid command is issued. when the ech command is followed by an 00h address cycle, the target goes busy for t r. if the read status (70h) command is used to monitor for command completion, the read mode (00h) command must be used to re-enable data output mode. use of the read status enhanced (78h) command is prohibited while the target is busy and during data output. after t r completes, the host enables data output mode to read the parameter page. when the asynchronous interface is active, one data byte is output per re# toggle. when the synchronous interface is active, one data byte is output for each rising or fall- ing edge of dqs. a minimum of three copies of the parameter page are stored in the device. each param- eter page is 256 bytes. if desired, the change read column (05h-e0h) command can be used to change the location of data output. use of the change read column enhanced (06h-e0h) command is prohibited. the read parameter page (ech) output data can be used by the host to configure its internal settings to properly use the nand flash device. parameter page data is stat- ic per part, however the value can be changed through the product cycle of nand flash. the host should interpret the data and configure itself accordingly. figure 39: read parameter (ech) operation cycle type dq[7:0] r/b# t wb t r t rr command address dout ech 00h p0 0 p1 0 dout dout p0 1 dout dout p1 1 dout micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read parameter page (ech) pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
parameter page data structure tables table 13: parameter page data structure byte description device values revision information and features block 0C3 parameter page signature byte 0: 4fh, o byte 1: 4eh, n byte 2: 46h, f byte 3: 49h, i C 4fh, 4eh, 46h, 49h 4C5 revision number bit[15:5]: reserved (0) bit 4: 1 = supports onfi verion 2.2 bit 3: 1 = supports onfi verion 2.1 bit 2: 1 = supports onfi version 2.0 bit 1: 1 = supports onfi version 1.0 bit 0: reserved (0) C 1eh, 00h 6C7 features supported bit[15:9]: reserved (0) bit 8: 1 = supports program page register clear enhance- ment bit 7: 1 = supports extended parameter page bit 6: 1 = supports interleaved (multi-plane) read opera- tions bit 5: 1 = supports synchronous interface bit 4: 1 = supports odd-to-even page copyback bit 3: 1 = supports interleaved (multi-plane) program and erase operations bit 2: 1 = supports non-sequential page programming bit 1: 1 = supports multiple lun operations bit 0: 1 = supports 16-bit data bus width mt29f32g08cbaca d8h, 01h mt29f64g08ceaca mt29f64g08cfaca MT29F128G08CXACA mt29f64g08ceccb f8h, 01h 8C9 optional commands supported bit[15:10]: reserved (0) bit 9: 1 = supports reset lun command bit 8: 1 = supports small data move bit 7: 1 = supports change row address bit 6: 1 = supports change read column enhanced bit 5: 1 = supports read unique id bit 4: 1 = supports copyback bit 3: 1 = supports read status enhanced bit 2: 1 = supports get features and set features bit 1: 1 = supports read cache commands bit 0: 1 = supports program page cache C ffh, 03h 10C11 reserved (0) C all 00h 12C13 extended parameter page length C 03h, 00h 14 number of parameter pages C 03h 15C31 reserved (0) C all 00h micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand parameter page data structure tables pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 13: parameter page data structure (continued) byte description device values manufacturer information block 32C43 device manufacturer (12 ascii characters) micron C 4dh, 49h, 43h, 52h, 4fh, 4eh, 20h, 20h, 20h, 20h, 20h, 20h 44C63 device model (20 ascii characters) mt29f32g08cbacawp 4dh, 54h, 32h, 39h, 46h, 33h, 32h, 47h, 30h, 38h, 43h, 42h, 41h, 43h, 41h, 57h, 50h, 20h, 20h, 20h mt29f64g08cfacawp 4dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 43h, 46h, 41h, 43h, 41h, 57h, 50h, 20h, 20h, 20h mt29f64g08ceacad1 4dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 43h, 45h, 41h, 43h, 41h, 44h, 31h, 20h, 20h, 20h MT29F128G08CXACAd1 4dh, 54h, 32h, 39h, 46h, 31h, 32h, 38h, 47h, 30h, 38h, 43h, 58h, 41h, 43h, 41h, 44h, 31h, 20h, 20h mt29f64g08ceccbh1 4dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 43h, 45h, 43h, 43h, 42h, 48h, 31h, 20h, 20h, 20h 64 jedec manufacturer id C 2ch 65C66 date code C 00h, 00h 67C79 reserved (0) C all 00h memory organization block 80C83 number of data bytes per page C 00h, 10h, 00h, 00h 84C85 number of spare bytes per page C e0h, 00h 86C91 reserved (0) C all 00h 92C95 number of pages per block 00h, 01h, 00h, 00h 96C99 number of blocks per lun C 00h, 10h, 00h, 00h 100 number of luns per chip enable mt29f32g08cbacawp 01h mt29f64g08cfacawp mt29f64g08ceacad1 MT29F128G08CXACAd1 mt29f64g08ceccbh1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand parameter page data structure tables pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 13: parameter page data structure (continued) byte description device values 101 number of address cycles bit[7:4]: column address cycles bit[3:0]: row address cycles C 23h 102 number of bits per cell C 02h 103C104 bad blocks maximum per lun C 64h, 00h 105C106 block endurance C 03h, 03h 107 guaranteed valid blocks at beginning of target C 01h 108C109 block endurance for guaranteed valid blocks C 00h, 00h 110 number of programs per page C 01h 111 partial programming attributes bit[7:5]: reserved bit 4: 1 = partial page layout is partial page data fol- lowed by partial page spare bit[3:1]: reserved bit 0: 1 = partial page programming has constraints C 00h 112 number of bits ecc correctability C ffh 113 number of interleaved address bits bit[7:4]: reserved (0) bit[3:0]: number of interleaved address bits C 01h 114 interleaved operation attributes bit[7:5]: reserved (0) bit 4: 1 = supports read cache bit 3: address restrictions for cache operations bit 2: 1 = supports program cache bit 1: 1 = no block address restrictions bit 0: overlapped/concurrent interleaving support C 1eh 115C127 reserved (0) C all 00h electrical parameters block 128 i/o pin capacitance per chip enable mt29f32g08cbacawp 05h mt29f64g08cfacawp 0ah mt29f64g08ceacad1 05h MT29F128G08CXACAd1 07h mt29f64g08ceccbh1 05h 129C130 timing mode support bit[15:6]: reserved (0) bit 5: 1 = supports timing mode 5 bit 4: 1 = supports timing mode 4 bit 3: 1 = supports timing mode 3 bit 2: 1 = supports timing mode 2 bit 1: 1 = supports timing mode 1 bit 0: 1 = supports timing mode 0, shall be 1 C 3fh, 00h 131C132 reserved (0) C all 00h 133C134 t prog maximum program page time (s) C 98h, 08h micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand parameter page data structure tables pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 13: parameter page data structure (continued) byte description device values 135C136 t bers maximum block erase time (s) C 10h, 27h 137C138 t r maximum page read time (s) C 32h, 00h 139C140 t ccs minimum change column setup time (ns) C c8h, 00h 141C142 source synchronous timing mode support bit[15:6]: reserved (0) bit 5: 1 = supports timing mode 5 bit 4: 1 = supports timing mode 4 bit 3: 1 = supports timing mode 3 bit 2: 1 = supports timing mode 2 bit 1: 1 = supports timing mode 1 bit 0: 1 = supports timing mode 0 mt29f32g08cbacawp 00h, 00h mt29f64g08cfacawp mt29f64g08ceacad1 MT29F128G08CXACAd1 mt29f64g08ceccbh1 3fh, 00h 143 source synchronous features bit[7:3]: reserved (0) bit 2: 1 = devices support clk stopped for data input bit 1: 1 = typical capacitance values present bit 0: 0 = use t cad min value mt29f32g08cbacawp 00h mt29f64g08cfacawp mt29f64g08ceacad1 MT29F128G08CXACAd1 mt29f64g08ceccbh1 02h 144C145 clk input pin capacitance, typical mt29f32g08cbacawp 00h, 00h mt29f64g08cfacawp mt29f64g08ceacad1 MT29F128G08CXACAd1 mt29f64g08ceccbh1 23h, 00h 146C147 i/o pin capacitance, typical mt29f32g08cbacawp 00h, 00h mt29f64g08cfacawp mt29f64g08ceacad1 MT29F128G08CXACAd1 mt29f64g08ceccbh1 2dh, 00h 148C149 input capacitance, typical mt29f32g08cbacawp 00h, 00h mt29f64g08cfacawp mt29f64g08ceacad1 MT29F128G08CXACAd1 mt29f64g08ceccbh1 28h, 00h 150 input pin capacitance, maximum mt29f32g08cbacawp 0ah mt29f64g08cfacawp 07h mt29f64g08ceacad1 08h MT29F128G08CXACAd1 05h mt29f64g08ceccbh1 05h micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand parameter page data structure tables pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 13: parameter page data structure (continued) byte description device values 151 driver strength support bit[7:3]: reserved (0) bit 2: 1 = supports overdrive 2 drive strength bit 1: 1 = supports overdrive 1 drive strength bit 0: 1 = supports driver strength settings C 07h 152C153 t r maximum interleaved (multi-plane) page read time (s) C 32h, 00h 154-155 t adl program register clear enhancement values (ns) C 46h, 00h 156C163 reserved (0) C all 00h vendor block 164C165 vendor-specific revision number C 01h, 00h 166 two-plane page read support bit[7:1]: reserved (0) bit 0: 1 = support for two-plane page read C 01h 167 read cache support bit[7:1]: reserved (0) bit 0: 0 = does not support micron-specific read cache function C 00h 168 read unique id support bit[7:1]: reserved (0) bit 0: 0 = does not support micron-specific read unique id C 00h 169 programmable dq output impedance support bit[7:1]: reserved (0) bit 0: 0 = no support for programmable dq output impe- dance by b8h command C 00h 170 number of programmable dq output impedance settings bit[7:3]: reserved (0) bit [2:0] = number of programmable dq output impe- dance settings C 04h 171 programmable dq output impedance feature address bit[7:0] = programmable dq output impedance feature address C 10h 172 programmable r/b# pull-down strength support bit[7:1]: reserved (0) bit 0: 1 = support programmable r/b# pull-down strength C 01h 173 programmable r/b# pull-down strength feature address bit[7:0] = feature address used with programmable r/b# pull-down strength C 81h 174 number of programmable r/b# pull-down strength set- tings bit[7:3]: reserved (0) bit[2:0] = number of programmable r/b# pull-down strength settings C 04h micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand parameter page data structure tables pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 13: parameter page data structure (continued) byte description device values 175 otp mode support bit[7:2]: reserved (0) bit 1: 1 = supports get/set features command set bit 0: 0 = does not support a5h/a0h/afh otp command set C 02h 176 otp page start bit[7:0] = page where otp page space begins C 02h 177 otp data protect address bit[7:0] = page address to use when issuing otp data protect command C 01h 178 number of otp pages bit[15:5]: reserved (0) bit[4:0] = number of otp pages C 1eh 179 otp feature address C 90h 180C252 reserved (0) C all 00h 253 parameter page revision C 01h 254C255 integrity crc mt29f32g08cbacawp 17h, e4h mt29f64g08cfacawp 16h, fbh mt29f64g08ceacad1 9ch, 63h MT29F128G08CXACAd1 8ch, e4h mt29f64g08ceccbh1 d1h, 76h redundant parameter pages 256C511 value of bytes 0C255 C see bytes 0C255 512C767 value of bytes 0C255 C see bytes 0C255 extended parameter pages 768C769 extended parameter page integrity crc C bch, 71h 770-773 extended parameter page signature byte 0: 45h, e byte 1: 50h, p byte 2: 50h, p byte 3: 53h, s C 45h, 50h, 50h, 53h 774-783 reserved (0) C all 00h 784 section 0 type C 02h 785 section 0 length C 01h 786-799 reserved (0) C all 00h 800 number of bits ecc correctability C 18h 801 ecc codeword size C 0ah 802-803 bad blocks maximum per lun C 64h, 00h 804-805 block endurance C 03h, 03h 806-815 reserved (0) C all 00h 816-863 value of bytes 768-815 C see bytes 768-815 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand parameter page data structure tables pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 13: parameter page data structure (continued) byte description device values 864-911 value of bytes 768-815 C see bytes 768-815 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand parameter page data structure tables pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
read unique id (edh) the read unique id (edh) command is used to read a unique identifier programmed into the target. this command is accepted by the target only when all die (luns) on the target are idle. writing edh to the command register puts the target in read unique id mode. the tar- get stays in this mode until another valid command is issued. when the edh command is followed by a 00h address cycle, the target goes busy for t r. if the read status (70h) command is used to monitor for command completion, the read mode (00h) command must be used to re-enable data output mode. after t r completes, the host enables data output mode to read the unique id. when the asynchronous interface is active, one data byte is output per re# toggle. when the syn- chronous interface is active, two data bytes are output, one byte for each rising or falling edge of dqs. sixteen copies of the unique id data are stored in the device. each copy is 32 bytes. the first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the comple- ment of the first 16 bytes. the host should xor the first 16 bytes with the second 16 bytes. if the result is 16 bytes of ffh, then that copy of the unique id data is correct. in the event that a non-ffh result is returned, the host can repeat the xor operation on a subsequent copy of the unique id data. if desired, the change read column (05h- e0h) command can be used to change the data output location. use of the change read column enhanced (06h-e0h) command is prohibited. figure 40: read unique id (edh) operation cycle type dq[7:0] r/b# t wb t r t rr command address dout edh 00h u0 0 u1 0 dout dout u0 1 dout dout u1 1 dout micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read unique id (edh) pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
status operations each die (lun) provides its status independently of other die (luns) on the same tar- get through its 8-bit status register. after the read status (70h) or read status enhanced (78h) command is issued, status register output is enabled. the contents of the status register are returned on dq[7:0] for each data output request. when the asynchronous interface is active and status register output is enabled, changes in the status register are seen on dq[7:0] as long as ce# and re# are low; it is not necessary to toggle re# to see the status register update. when the synchronous interface is active and status register output is enabled, changes in the status register are seen on dq[7:0] as long as ce# and w/r# are low and ale and cle are high. dqs also toggles while ale and cle are high. while monitoring the status register to determine when a data transfer from the flash array to the data register ( t r) is complete, the host must issue the read mode (00h) command to disable the status register and enable data output (see read mode (00h) (page 75)). the read status (70h) command returns the status of the most recently selected die (lun). to prevent data contention during or following an interleaved die (multi-lun) operation, the host must enable only one die (lun) for status output by using the read status enhanced (78h) command (see interleaved die (multi-lun) operations (page 100)). table 14: status register definition sr bit definition independent per plane 1 description 7 wp# C write protect: 0 = protected 1 = not protected in the normal array mode, this bit indicates the value of the wp# signal. in otp mode this bit is set to 0 if a program otp page operation is attemp- ted and the otp area is protected. 6 rdy C ready/busy i/o: 0 = busy 1 = ready this bit indicates that the selected die (lun) is not available to accept new commands, address, or data i/o cycles with the exception of reset (ffh), synchronous reset (fch), read status (70h), and read status en- hanced (78h). this bit applies only to the selected die (lun). 5 ardy C ready/busy array: 0 = busy 1 = ready this bit goes low (busy) when an array operation is occurring on any plane of the selected die (lun). it goes high when all array operations on the selected die (lun) finish. this bit applies only to the selected die (lun). 4 C C reserved (0) 3 C C reserved (0) micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand status operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 14: status register definition (continued) sr bit definition independent per plane 1 description 2 C C reserved (0) 1 failc yes pass/fail (C1): 0 = pass 1 = fail this bit is set if the previous operation on the selected die (lun) failed. this bit is valid only when rdy (sr bit 6) is 1. it applies to program-, and copy- back program-series operations (80h-10h, 80h-15h, 85h-10h). this bit is not valid following an erase-series or read-series operation. 0 fail yes pass/fail (n): 0 = pass 1 = fail this bit is set if the most recently finished operation on the selected die (lun) failed. this bit is valid only when ardy (sr bit 5) is 1. it applies to program-, erase-, and copyback program-series operations (80h-10h, 80h-15h, 60h-d0h, 85h-10h). this bit is not valid following a read-series operation. note: 1. after a multi-plane operation begins, the failc and fail bits are ored together for the active planes when the read status (70h) command is issued. after the read status enhanced (78h) command is issued, the failc and fail bits reflect the status of the plane selected. read status (70h) the read status (70h) command returns the status of the last-selected die (lun) on a target. this command is accepted by the last-selected die (lun) even when it is busy (rdy = 0). if there is only one die (lun) per target, the read status (70h) command can be used to return status following any nand command. in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations, the read status enhanced (78h) command must be used to select the die (lun) that should report status. in this situation, using the read status (70h) command will result in bus contention, as two or more die (luns) could respond until the next operation is issued. the read status (70h) com- mand can be used following all single die (lun) operations. if following a multi-plane operation, regardless of the number of luns per target, the read status (70h) command indicates an error occurred (fail = 1), use the read status enhanced (78h) commandonce for each planeto determine which plane operation failed. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand status operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 41: read status (70h) operation cycle type dq[7:0] t whr command dout 70h sr read status enhanced (78h) the read status enhanced (78h) command returns the status of the addressed die (lun) on a target even when it is busy (rdy = 0). this command is accepted by all die (luns), even when they are busy (rdy = 0). writing 78h to the command register, followed by three row address cycles containing the page, block, and lun addresses, puts the selected die (lun) into read status mode. the selected die (lun) stays in this mode until another valid command is issued. die (luns) that are not addressed are deselected to avoid bus contention. the selected lun's status is returned when the host requests data output. the rdy and ardy bits of the status register are shared for all of the planes of the selected die (lun). the failc and fail bits are specific to the plane specified in the row address. the read status enhanced (78h) command also enables the selected die (lun) for data output. to begin data output following a read-series operation after the selected die (lun) is ready (rdy = 1), issue the read mode (00h) command, then begin data output. if the host needs to change the cache register that will output data, use the change read column enhanced (06h-e0h) command after the die (lun) is ready (see change read column enhanced (06h-e0h) (page 69)). use of the read status enhanced (78h) command is prohibited during the power- on reset (ffh) command and when otp mode is enabled. it is also prohibited follow- ing some of the other reset, identification, and configuration operations. see individual operations for specific details. figure 42: read status enhanced (78h) operation cycle type dqx t whr command address address address 78h r1 r2 r3 dout sr micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand status operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
column address operations the column address operations affect how data is input to and output from the cache registers within the selected die (luns). these features provide host flexibility for man- aging data, especially when the host internal buffer is smaller than the number of data bytes or words in the cache register. when the asynchronous interface is active, column address operations can address any byte in the selected cache register. when the synchronous interface is active, column address operations are aligned to word boundaries (ca0 is forced to 0), because as data is transferred on dq[7:0] in two- byte units. change read column (05h-e0h) the change read column (05h-e0h) command changes the column address of the selected cache register and enables data output from the last selected die (lun). this command is accepted by the selected die (lun) when it is ready (rdy = 1; ardy = 1). it is also accepted by the selected die (lun) during cache read operations (rdy = 1; ardy = 0). writing 05h to the command register, followed by two column address cycles contain- ing the column address, followed by the e0h command, puts the selected die (lun) into data output mode. after the e0h command cycle is issued, the host must wait at least t ccs before requesting data output. the selected die (lun) stays in data output mode until another valid command is issued. in devices with more than one die (lun) per target, during and following interleaved die (multi-lun) operations, the read status enhanced (78h) command must be issued prior to issuing the change read column (05h-e0h). in this situation, using the change read column (05h-e0h) command without the read status en- hanced (78h) command will result in bus contention, as two or more die (luns) could output data. figure 43: change read column (05h-e0h) operation cycle type dq[7:0] sr[6] command address address 05h command e0h c1 c2 t ccs t rhw d out dk d out dk + 1 d out dk + 2 d out dn d out dn + 1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand column address operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
change read column enhanced (06h-e0h) the change read column enhanced (06h-e0h) command enables data output on the addressed dies (luns) cache register at the specified column address. this com- mand is accepted by a die (lun) when it is ready (rdy = 1; ardy = 1). writing 06h to the command register, followed by two column address cycles and three row address cycles, followed by e0h, enables data output mode on the address luns cache register at the specified column address. after the e0h command cycle is issued, the host must wait at least t ccs before requesting data output. the selected die (lun) stays in data output mode until another valid command is issued. following a multi-plane read page operation, the change read column en- hanced (06h-e0h) command is used to select the cache register to be enabled for data output. after data output is complete on the selected plane, the command can be is- sued again to begin data output on another plane. in devices with more than one die (lun) per target, after all of the die (luns) on the target are ready (rdy = 1), the change read column enhanced (06h-e0h) com- mand can be used following an interleaved die (multi-lun) read operation. die (luns) that are not addressed are deselected to avoid bus contention. in devices with more than one die (lun) per target, during interleaved die (multi-lun) operations where more than one or more die (luns) are busy (rdy = 1; ardy = 0 or rdy = 0; ardy = 0), the read status enhanced (78h) command must be issued to the die (lun) to be selected prior to issuing the change read column enhanced (06h-e0h). in this situation, using the change read column enhanced (06h-e0h) command without the read status enhanced (78h) command will result in bus contention, as two or more die (luns) could output data. if there is a need to update the column address without selecting a new cache register or lun, the change read column (05h-e0h) command can be used instead. figure 44: change read column enhanced (06h-e0h) operation cycle type dq[7:0] command address address 06h command e0h c1 c2 address address r1 r2 address r3 t ccs t rhw dout dk dout dk + 1 dout dk + 2 dout dn dout dn + 1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand column address operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
change write column (85h) the change write column (85h) command changes the column address of the se- lected cache register and enables data input on the last-selected die (lun). this com- mand is accepted by the selected die (lun) when it is ready (rdy = 1; ardy = 1). it is also accepted by the selected die (lun) during cache program operations (rdy = 1; ardy = 0). writing 85h to the command register, followed by two column address cycles contain- ing the column address, puts the selected die (lun) into data input mode. after the second address cycle is issued, the host must wait at least t ccs before inputting data. the selected die (lun) stays in data input mode until another valid command is issued. though data input mode is enabled, data input from the host is optional. data input begins at the column address specified. the change write column (85h) command is allowed after the required address cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the follow- ing commands while data input is permitted: program page (80h-10h), program page multi-plane (80h-11h), program page cache (80h-15h), copyback pro- gram (85h-10h), and copyback program multi-plane (85h-11h). in devices that have more than one die (lun) per target, the change write col- umn (85h) command can be used with other commands that support interleaved die (multi-lun) operations. figure 45: change write column (85h) operation cycle type dq[7:0] rdy command address address 85h c1 c2 t ccs d in dk d in dk + 1 d in dk + 2 d in dn d in dn + 1 as defined for page (cache) program as defined for page (cache) program micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand column address operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
change row address (85h) the change row address (85h) command changes the row address (block and page) where the cache register contents will be programmed in the nand flash array. it also changes the column address of the selected cache register and enables data input on the specified die (lun). this command is accepted by the selected die (lun) when it is ready (rdy = 1; ardy = 1). it is also accepted by the selected die (lun) during cache programming operations (rdy = 1; ardy = 0). write 85h to the command register. then write two column address cycles and three row address cycles. this updates the page and block destination of the selected plane for the addressed lun and puts the cache register into data input mode. after the fifth address cycle is issued the host must wait at least t ccs before inputting data. the selec- ted lun stays in data input mode until another valid command is issued. though data input mode is enabled, data input from the host is optional. data input begins at the column address specified. the change row address (85h) command is allowed after the required address cy- cles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following commands while data input is permitted: program page (80h-10h), program page multi-plane (80h-11h), program page cache (80h-15h), copyback program (85h-10h), and copyback program multi-plane (85h-11h). when used with these commands, the lun address and plane select bits are required to be identical to the lun address and plane select bits originally specified. the change row address (85h) command enables the host to modify the original page and block address for the data in the cache register to a new page and block address. in devices that have more than one die (lun) per target, the change row address (85h) command can be used with other commands that support interleaved die (multi- lun) operations. the change row address (85h) command can be used with the change read column (05h-e0h) or change read column enhanced (06h-e0h) commands to read and modify cache register contents in small sections prior to programming cache register contents to the nand flash array. this capability can reduce the amount of buffer memory used in the host controller. to modify the cache register contents in small sections, first issue a page read (00h-30h) or copyback read (00h-35h) operation. when data output is enabled, the host can output a portion of the cache register contents. to modify the cache register contents, issue the 85h command, the column and row addresses, and input the new data. the host can re-enable data output by issuing the 11h command, waiting t dbsy, and then issuing the change read column (05h-e0h) or change read column enhanced (06h-e0h) command. it is possible toggle between data output and data input multiple times. after the final change row address (85h) operation is com- plete, issue the 10h command to program the cache register to the nand flash array. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand column address operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 46: change row address (85h) operation cycle type dq[7:0] rdy command address address address address address 85h c1 c2 t ccs d in dk d in dk + 1 d in dk + 2 d in dn d in dn + 1 as defined for page (cache) program as defined for page (cache) program r1 r2 r3 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand column address operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
read operations read operations are used to copy data from the nand flash array of one or more of the planes to their respective cache registers and to enable data output from the cache reg- isters to the host through the dq bus. read operations the read page (00h-30h) command, when issued by itself, reads one page from the nand flash array to its cache register and enables data output for that cache register. during data output the following commands can be used to read and modify the data in the cache registers: change read column (05h-e0h) and change row ad- dress (85h). read cache operations to increase data throughput, the read page cache-series (31h, 00h-31h) commands can be used to output data from the cache register while concurrently copying a page from the nand flash array to the data register. to begin a read page cache sequence, begin by reading a page from the nand flash array to its corresponding cache register using the read page (00h-30h) command. r/b# goes low during t r and the selected die (lun) is busy (rdy = 0, ardy = 0). after t r (r/b# is high and rdy = 1, ardy = 1), issue either of these commands: ? read page cache sequential (31h)copies the next sequential page from the nand flash array to the data register ? read page cache random (00h-31h)copies the page specified in this com- mand from the nand flash array (any plane) to its corresponding data register after the read page cache-series (31h, 00h-31h) command has been issued, r/b# goes low on the target, and rdy = 0 and ardy = 0 on the die (lun) for t rcbsy while the next page begins copying data from the array to the data register. after t rcbsy, r/b# goes high and the dies (luns) status register bits indicate the device is busy with a cache operation (rdy = 1, ardy = 0). the cache register becomes available and the page requested in the read page cache operation is transferred to the data regis- ter. at this point, data can be output from the cache register, beginning at column address 0. the change read column (05h-e0h) command can be used to change the column address of the data output by the die (lun). after outputting the desired number of bytes from the cache register, either an addition- al read page cache-series (31h, 00h-31h) operation can be started or the read page cache last (3fh) command can be issued. if the read page cache last (3fh) command is issued, r/b# goes low on the tar- get, and rdy = 0 and ardy = 0 on the die (lun) for t rcbsy while the data register is copied into the cache register. after t rcbsy, r/b# goes high and rdy = 1 and ardy = 1, indicating that the cache register is available and that the die (lun) is ready. data can then be output from the cache register, beginning at column address 0. the change read column (05h-e0h) command can be used to change the column ad- dress of the data being output. for read page cache-series (31h, 00h-31h, 3fh), during the die (lun) busy time, t rcbsy, when rdy = 0 and ardy = 0, the only valid commands are status operations (70h, 78h) and reset (ffh, fch). when rdy = 1 and ardy = 0, the only valid com- mands during read page cache-series (31h, 00h-31h) operations are status opera- micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
tions (70h, 78h), read mode (00h), read page cache-series (31h, 00h-31h), change read column (05h-e0h), and reset (ffh, fch). multi-plane read operations multi-plane read page operations improve data throughput by copying data from more than one plane simultaneously to the specified cache registers. this is done by prepend- ing one or more read page multi-plane (00h-32h) commands in front of the read page (00h-30h) command. when the die (lun) is ready, the change read column enhanced (06h-e0h) com- mand determines which plane outputs data. during data output, the following com- mands can be used to read and modify the data in the cache registers: change read column (05h-e0h) and change row address (85h). see multi-plane operations for details. multi-plane read cache operations multi-plane read cache operations can be used to output data from more than one cache register while concurrently copying one or more pages from the nand flash ar- ray to the data register. this is done by prepending read page multi-plane (00h-32h) commands in front of the page read cache random (00h-31h) command. to begin a multi-plane read page cache sequence, begin by issuing a multi-plane read page operation using the read page multi-plane (00h-32h) and read page (00h-30h) commands. r/b# goes low during t r and the selected die (lun) is busy (rdy = 0, ardy = 0). after t r (r/b# is high and rdy = 1, ardy = 1), issue either of these commands: ? read page cache sequential (31h)copies the next sequential page from the previously addressed planes from the nand flash array to the data registers. ? read page multi-plane (00h-32h) commands, if desired, followed by the read page cache random (00h-31h) commandcopies the pages specified from the nand flash array to the corresponding data registers. after the read page cache-series (31h, 00h-31h) command has been issued, r/b# goes low on the target, and rdy = 0 and ardy = 0 on the die (lun) for t rcbsy while the next pages begin copying data from the array to the data registers. after t rcbsy, r/b# goes high and the luns status register bits indicate the device is busy with a cache operation (rdy = 1, ardy = 0). the cache registers become available and the pa- ges requested in the read page cache operation are transferred to the data registers. issue the change read column enhanced (06h-e0h) command to determine which cache register will output data. after data is output, the change read col- umn enhanced (06h-e0h) command can be used to output data from other cache registers. after a cache register has been selected, the change read column (05h- e0h) command can be used to change the column address of the data output. after outputting data from the cache registers, either an additional multi-plane read cache-series (31h, 00h-31h) operation can be started or the read page cache last (3fh) command can be issued. if the read page cache last (3fh) command is issued, r/b# goes low on the tar- get, and rdy = 0 and ardy = 0 on the die (lun) for t rcbsy while the data registers are copied into the cache registers. after t rcbsy, r/b# goes high and rdy = 1 and ardy = 1, indicating that the cache registers are available and that the die (lun) is ready. issue the change read column enhanced (06h-e0h) command to determine which micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
cache register will output data. after data is output, the change read column en- hanced (06h-e0h) command can be used to output data from other cache registers. after a cache register has been selected, the change read column (05h-e0h) com- mand can be used to change the column address of the data output. for read page cache-series (31h, 00h-31h, 3fh), during the die (lun) busy time, t rcbsy, when rdy = 0 and ardy = 0, the only valid commands are status operations (70h, 78h) and reset (ffh, fch). when rdy = 1 and ardy = 0, the only valid com- mands during read page cache-series (31h, 00h-31h) operations are status opera- tions (70h, 78h), read mode (00h), multi-plane read cache-series (31h, 00h-32h, 00h-31h), change read column (05h-e0h, 06h-e0h), and reset (ffh, fch). see multi-plane operations for additional multi-plane addressing requirements. read mode (00h) the read mode (00h) command disables status output and enables data output for the last-selected die (lun) and cache register after a read operation (00h-30h, 00h-35h) has been monitored with a status operation (70h, 78h). this command is ac- cepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) during read page cache (31h, 3fh, 00h-31h) operations (rdy = 1 and ardy = 0). in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations, the read status enhanced (78h) command must be used to select only one die (lun) prior to issuing the read mode (00h) com- mand. this prevents bus contention. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
read page (00h-30h) the read page (00hC30h) command copies a page from the nand flash array to its respective cache register and enables data output. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). to read a page from the nand flash array, write the 00h command to the command register, the write five address cycles to the address registers, and conclude with the 30h command. the selected die (lun) will go busy (rdy = 0, ardy = 0) for t r as data is transferred. to determine the progress of the data transfer, the host can monitor the target's r/b# signal or, alternatively, the status operations (70h, 78h) can be used. if the status opera- tions are used to monitor the lun's status, when the die (lun) is ready (rdy = 1, ardy = 1), the host disables status output and enables data output by issuing the read mode (00h) command. when the host requests data output, output begins at the column address specified. during data output the change read column (05h-e0h) command can be issued. in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations the read status enhanced (78h) command must be used to select only one die (lun) prior to the issue of the read mode (00h) command. this prevents bus contention. the read page (00h-30h) command is used as the final command of a multi-plane read operation. it is preceded by one or more read page multi-plane (00h-32h) commands. data is transferred from the nand flash array for all of the addressed planes to their respective cache registers. when the die (lun) is ready (rdy = 1, ardy = 1), data output is enabled for the cache register linked to the plane addressed in the read page (00h-30h) command. when the host requests data output, output begins at the column address last specified in the read page (00h-30h) com- mand. the change read column enhanced (06h-e0h) command is used to enable data output in the other cache registers. see multi-plane operations for addition- al multi-plane addressing requirements. figure 47: read page (00h-30h) operation cycle type dq[7:0] rdy command address address address address address command t wb t r t rr 00h c1 c2 r1 r2 r3 30h dout d n dout d n+1 dout d n+2 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
read page cache sequential (31h) the read page cache sequential (31h) command reads the next sequential page within a block into the data register while the previous page is output from the cache register. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). to issue this command, write 31h to the command register. after this command is is- sued, r/b# goes low and the die (lun) is busy (rdy = 0, ardy = 0) for t rcbsy. after t rcbsy, r/b# goes high and the die (lun) is busy with a cache operation (rdy = 1, ardy = 0), indicating that the cache register is available and that the specified page is copying from the nand flash array to the data register. at this point, data can be output from the cache register beginning at column address 0. the change read column (05h-e0h) command can be used to change the column address of the data being output from the cache register. the read page cache sequential (31h) command can be used to cross block boun- daries. if the read page cache sequential (31h) command is issued after the last page of a block is read into the data register, the next page read will be the next logical block in the plane which the 31h command was issued. do not issue the read page cache sequential (31h) to cross die (lun) boundaries. instead, issue the read page cache last (3fh) command. if the read page cache sequential (31h) command is issued after a multi- plane read page operation (00h-32h, 00h-30h), the next sequential pages are read into the data registers while the previous pages can be output from the cache registers. after the die (lun) is ready (rdy = 1, ardy = 0), the change read column en- hanced (06h-e0h) command is used to select which cache register outputs data. figure 48: read page cache sequential (31h) operation cycle type dq[7:0] rdy t wb t rcbsy t rr command d out d out d out command d out 31h t wb command 30h t wb t rcbsy t rr d0 dn 31h d0 command address x5 00h page address m page m page m+1 t r micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
read page cache random (00h-31h) the read page cache random (00h-31h) command reads the specified block and page into the data register while the previous page is output from the cache register. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). to issue this command, write 00h to the command register, then write five address cy- cles to the address register, and conclude by writing 31h to the command register. the column address in the address specified is ignored. the die (lun) address must match the same die (lun) address as the previous read page (00h-30h) command or, if ap- plicable, the previous read page cache random (00h-31h) command. there is no restriction on the plane address. after this command is issued, r/b# goes low and the die (lun) is busy (rdy = 0, ardy = 0) for t rcbsy. after t rcbsy, r/b# goes high and the die (lun) is busy with a cache operation (rdy = 1, ardy = 0), indicating that the cache register is available and that the specified page is copying from the nand flash array to the data register. at this point, data can be output from the cache register beginning at column address 0. the change read column (05h-e0h) command can be used to change the column address of the data being output from the cache register. in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations the read status enhanced (78h) command followed by the read mode (00h) command must be used to select only one die (lun) and prevent bus contention. if a multi-plane cache random (00h-32h, 00h-31h) command is issued after a multi-plane read page operation (00h-32h, 00h-30h), then the addressed pages are read into the data registers while the previous pages can be output from the cache registers. after the die (lun) is ready (rdy = 1, ardy = 0), the change read col- umn enhanced (06h-e0h) command is used to select which cache register outputs data. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 49: read page cache random (00h-31h) operation cycle type dq[7:0] rdy t wb t rcbsy t rr command d out d out d out 31h t wb command 30h d0 dn command address x5 00h command 00h page address m address x5 page address n command 00h page m t r 1 cycle type dq[7:0] rdy d out command d out t wb t rcbsy t rr dn 31h d0 command 00h address x5 page address p page n 1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
read page cache last (3fh) the read page cache last (3fh) command ends the read page cache sequence and copies a page from the data register to the cache register. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) during read page cache (31h, 00h-31h) operations (rdy = 1 and ardy = 0). to issue the read page cache last (3fh) command, write 3fh to the command reg- ister. after this command is issued, r/b# goes low and the die (lun) is busy (rdy = 0, ardy = 0) for t rcbsy. after t rcbsy, r/b# goes high and the die (lun) is ready (rdy = 1, ardy = 1). at this point, data can be output from the cache register, beginning at column address 0. the change read column (05h-e0h) command can be used to change the column address of the data being output from the cache register. in devices that have more than one lun per target, during and following interleaved die (multi-lun) operations the read status enhanced (78h) command followed by the read mode (00h) command must be used to select only one die (lun) and prevent bus contention. if the read page cache last (3fh) command is issued after a multi-plane read page cache operation (31h; 00h-32h, 00h-30h), the die (lun) goes busy until the pa- ges are copied from the data registers to the cache registers. after the die (lun) is ready (rdy = 1, ardy = 1), the change read column enhanced (06h-e0h) command is used to select which cache register outputs data. figure 50: read page cache last (3fh) operation cycle type dq[7:0] rdy t wb t rcbsy t rr command d out d out d out command d out d out d out 31h t wb t rcbsy t rr d0 d0 dn as defined for read page cache (sequential or random) dn 3fh page n page address n micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
read page multi-plane (00h-32h) the read page multi-plane (00h-32h) command queues a plane to transfer data from the nand flash array to its cache register. this command can be issued one or more times. each time a new plane address is specified, that plane is also queued for data transfer. the read page (00h-30h) command is issued to select the final plane and to begin the read operation for all previously queued planes. all queued planes will transfer data from the nand flash array to their cache registers. to issue the read page multi-plane (00h-32h) command, write 00h to the com- mand register, then write five address cycles to the address register, and conclude by writing 32h to the command register. the column address in the address specified is ignored. after this command is issued, r/b# goes low and the die (lun) is busy (rdy = 0, ardy = 0) for t dbsy. after t dbsy, r/b# goes high and the die (lun) is ready (rdy = 1, ardy = 1). at this point, the die (lun) and block are queued for data transfer from the array to the cache register for the addressed plane. during t dbsy, the only val- id commands are status operations (70h, 78h) and reset commands (ffh, fch). follow- ing t dbsy, to continue the multi-plane read operation, the only valid commands are status operations (70h, 78h), read page multi-plane (00h-32h), read page (00h-30h), and read page cache random (00h-31h). additional read page multi-plane (00h-32h) commands can be issued to queue additional planes for data transfer. if the read page (00h-30h) command is used as the final command of a multi- plane read operation, data is transferred from the nand flash array for all of the addressed planes to their respective cache registers. when the die (lun) is ready (rdy = 1, ardy = 1), data output is enabled for the cache register linked to the plane addressed in the read page (00h-30h) command. when the host requests data output, it begins at the column address specified in the read page (00h-30h) command. to enable data output in the other cache registers, use the change read column en- hanced (06h-e0h) command. additionally, the change read column (05h-e0h) command can be used to change the column address within the currently selected plane. if the read page cache sequential (31h) is used as the final command of a multi- plane read cache operation, data is copied from the previously read operation from each plane to each cache register and then data is transferred from the nand flash array for all previously addressed planes to their respective data registers. when the die (lun) is ready (rdy = 1, ardy = 0), data output is enabled. the change read col- umn enhanced (06h-e0h) command is used to determine which cache register outputs data first. to enable data output in the other cache registers, use the change read column enhanced (06h-e0h) command. additionally, the change read column (05h-e0h) command can be used to change the column address within the currently selected plane. if the read page cache random (00h-31h) command is used as the final command of a multi-plane read cache operation, data is copied from the previously read operation from the data register to the cache register and then data is transferred from the nand flash array for all of the addressed planes to their respective data registers. when the die (lun) is ready (rdy = 1, ardy = 0), data output is enabled. the change read column enhanced (06h-e0h) command is used to determine which cache register outputs data first. to enable data output in the other cache registers, use the change read column enhanced (06h-e0h) command. additionally, the micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
change read column (05h-e0h) command can be used to change the column ad- dress within the currently selected plane. see multi-plane operations for additional multi-plane addressing requirements. figure 51: read page multi-plane (00h-32h) operation cycle type dq[7:0] rdy command address address address address address command t wb t dbsy 00h c1 c2 command address address 00h c1 ... r1 r2 r3 32h micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand read operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
program operations program operations are used to move data from the cache or data registers to the nand array of one or more planes. during a program operation the contents of the cache and/or data registers are modified by the internal control logic. within a block, pages must be programmed sequentially from the least significant page address to the most significant page address (i.e. 0, 1, 2, 3, ). programming pages out of order within a block is prohibited. program operations the program page (80h-10h) command, when not preceded by the program page multi-plane (80h-11h) command, programs one page from the cache register to the nand flash array. when the die (lun) is ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that the operation has completed successfully. program cache operations the program page cache (80h-15h) command can be used to improve program op- eration system performance. when this command is issued, the die (lun) goes busy (rdy = 0, ardy = 0) while the cache register contents are copied to the data register, and the die (lun) is busy with a program cache operation (rdy = 1, ardy = 0. while the contents of the data register are moved to the nand flash array, the cache register is available for an additional program page cache (80h-15h) or program page (80h-10h) command. for program page cache-series (80h-15h) operations, during the die (lun) busy times, t cbsy and t lprog, when rdy = 0 and ardy = 0, the only valid commands are status operations (70h, 78h) and reset (ffh, fch). when rdy = 1 and ardy = 0, the only valid commands during program page cache-series (80h-15h) operations are sta- tus operations (70h, 78h), program page cache (80h-15h), program page (80h-10h), change write column (85h), change row address (85h), and reset (ffh, fch). multi-plane program operations the program page multi-plane (80h-11h) command can be used to improve pro- gram operation system performance by enabling multiple pages to be moved from the cache registers to different planes of the nand flash array. this is done by prepending one or more program page multi-plane (80h-11h) commands in front of the pro- gram page (80h-10h) command. see multi-plane operations for details. multi-plane program cache operations the program page multi-plane (80h-11h) command can be used to improve pro- gram cache operation system performance by enabling multiple pages to be moved from the cache registers to the data registers and, while the pages are being transferred from the data registers to different planes of the nand flash array, free the cache regis- ters to receive data input from the host. this is done by prepending one or more program page multi-plane (80h-11h) commands in front of the program page cache (80h-15h) command. see multi-plane operations for details. program page (80h-10h) the program page (80h-10h) command enables the host to input data to a cache register, and moves the data from the cache register to the specified block and page ad- micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand program operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
dress in the array of the selected die (lun). this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). it is also accepted by the die (lun) when it is busy with a program page cache (80h-15h) operation (rdy = 1, ardy = 0). to input a page to the cache register and move it to the nand array at the block and page address specified, write 80h to the command register. unless this command has been preceded by a program page multi-plane (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. then write five address cycles containing the column address and row address. data input cycles follow. serial data is input beginning at the column address specified. at any time during the data input cycle the change write column (85h) and change row address (85h) commands may be issued. when data input is com- plete, write 10h to the command register. the selected lun will go busy (rdy = 0, ardy = 0) for t prog as data is transferred. to determine the progress of the data transfer, the host can monitor the target's r/b# signal or, alternatively, the status operations (70h, 78h) may be used. when the die (lun) is ready (rdy = 1, ardy = 1), the host should check the status of the fail bit. in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations, the read status enhanced (78h) command must be used to select only one die (lun) for status output. use of the read status (70h) command could cause more than one die (lun) to respond, resulting in bus con- tention. the program page (80h-10h) command is used as the final command of a multi- plane program operation. it is preceded by one or more program page multi- plane (80h-11h) commands. data is transferred from the cache registers for all of the addressed planes to the nand array. the host should check the status of the operation by using the status operations (70h, 78h). see multi-plane operations for multi-plane addressing requirements. figure 52: program page (80h-10h) operation cycle type dq[7:0] rdy t adl command address address address address address 80h command 10h command 70h c1 c2 r1 r2 r3 din din din din d0 d1 dn dout status t wb t prog micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand program operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
program page cache (80h-15h) the program page cache (80h-15h) command enables the host to input data to a cache register; copies the data from the cache register to the data register; then moves the data register contents to the specified block and page address in the array of the selected die (lun). after the data is copied to the data register, the cache register is avail- able for additional program page cache (80h-15h) or program page (80h-10h) commands. the program page cache (80h-15h) command is accepted by the die (lun) when it is ready (rdy =1, ardy = 1). it is also accepted by the die (lun) when busy with a program page cache (80h-15h) operation (rdy = 1, ardy = 0). to input a page to the cache register to move it to the nand array at the block and page address specified, write 80h to the command register. unless this command has been preceded by a program page multi-plane (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. then write five address cycles containing the column address and row address. data input cycles follow. serial data is input beginning at the column address specified. at any time during the data input cycle the change write column (85h) and change row address (85h) commands may be issued. when data input is com- plete, write 15h to the command register. the selected lun will go busy (rdy = 0, ardy = 0) for t cbsy to allow the data register to become available from a previous program cache operation, to copy data from the cache register to the data reg- ister, and then to begin moving the data register contents to the specified page and block address. to determine the progress of t cbsy, the host can monitor the target's r/b# signal or, alternatively, the status operations (70h, 78h) can be used. when the luns status shows that it is busy with a program cache operation (rdy = 1, ardy = 0), the host should check the status of the failc bit to see if a previous cache operation was successful. if, after t cbsy, the host wants to wait for the program cache operation to complete, with- out issuing the program page (80h-10h) command, the host should monitor ardy until it is 1. the host should then check the status of the fail and failc bits. in devices with more than one die (lun) per target, during and following interleaved die (multi-lun) operations, the read status enhanced (78h) command must be used to select only one die (lun) for status output. use of the read status (70h) com- mand could cause more than one die (lun) to respond, resulting in bus contention. the program page cache (80h-15h) command is used as the final command of a multi-plane program cache operation. it is preceded by one or more program page multi-plane (80h-11h) commands. data for all of the addressed planes is transferred from the cache registers to the corresponding data registers, then moved to the nand flash array. the host should check the status of the operation by using the status opera- tions (70h, 78h). see multi-plane operations for multi-plane addressing requirements. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand program operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 53: program page cache (80hC15h) operation (start) cycle type dq[7:0] rdy t adl command address address address address address 80h c1 c2 r1 r2 r3 din din din din command d0 d1 dn 15h 1 t wb t cbsy cycle type dq[7:0] rdy t adl command address address address address address 80h c1 c2 r1 r2 r3 din din din din command d0 d1 dn 15h 1 t wb t cbsy figure 54: program page cache (80hC15h) operation (end) cycle type dq[7:0] rdy t adl command address address address address address 80h c1 c2 r1 r2 r3 din din din din command d0 d1 dn 15h 1 t wb t cbsy cycle type rdy t adl command address as defined for page cache program address address address address 80h c1 c2 r1 r2 r3 din din din din command d0 d1 dn 10h 1 t wb t lprog dq[7:0] micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand program operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
program page multi-plane 80h-11h the program page multi-plane (80h-11h) command enables the host to input da- ta to the addressed plane's cache register and queue the cache register to ultimately be moved to the nand flash array. this command can be issued one or more times. each time a new plane address is specified that plane is also queued for data transfer. to in- put data for the final plane and to begin the program operation for all previously queued planes, issue either the program page (80h-10h) command or the program page cache (80h-15h) command. all of the queued planes will move the data to the nand flash array. this command is accepted by the die (lun) when it is ready (rdy = 1). to input a page to the cache register and queue it to be moved to the nand flash array at the block and page address specified, write 80h to the command register. unless this command has been preceded by a program page multi-plane (80h-11h) com- mand, issuing the 80h to the command register clears all of the cache registers' con- tents on the selected target. write five address cycles containing the column address and row address; data input cycles follow. serial data is input beginning at the column address specified. at any time during the data input cycle, the change write col- umn (85h) and change row address (85h) commands can be issued. when data input is complete, write 11h to the command register. the selected die (lun) will go busy (rdy = 0, ardy = 0) for t dbsy. to determine the progress of t dbsy, the host can monitor the target's r/b# signal or, alternatively, the status operations (70h, 78h) can be used. when the lun's status shows that it is ready (rdy = 1), additional program page multi-plane (80h-11h) commands can be issued to queue additional planes for data transfer. alternatively, the program page (80h-10h) or program page cache (80h-15h) commands can be issued. when the program page (80h-10h) command is used as the final command of a multi- plane program operation, data is transferred from the cache registers to the nand flash array for all of the addressed planes during t prog. when the die (lun) is ready (rdy = 1, ardy = 1), the host should check the status of the fail bit for each of the planes to verify that programming completed successfully. when the program page cache (80h-15h) command is used as the final command of a multi-plane program cache operation, data is transferred from the cache registers to the data registers after the previous array operations finish. the data is then moved from the data registers to the nand flash array for all of the addressed planes. this occurs during t cbsy. after t cbsy, the host should check the status of the failc bit for each of the planes from the previous program cache operation, if any, to verify that programming completed successfully. for the program page multi-plane (80h-11h), program page (80h-10h), and program page cache (80h-15h) commands, see multi-plane operations for multi- plane addressing requirements. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand program operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 87 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 55: program page multi-plane (80hC11h) operation cycle type dq[7:0] rdy t adl command address address address address address 80h c1 command address 80h ... c2 r1 r2 r3 din din din command d0 dn 11h t wb t dbsy micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand program operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 88 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
erase operations erase operations are used to clear the contents of a block in the nand flash array to prepare its pages for program operations. erase operations the erase block (60h-d0h) command, when not preceded by the erase block mul- ti-plane (60h-d1h) command, erases one block in the nand flash array. when the die (lun) is ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that this operation completed successfully. multi-plane erase operations the erase block multi-plane (60h-d1h) command can be used to further system performance of erase operations by allowing more than one block to be erased in the nand array. this is done by prepending one or more erase block multi-plane (60h- d1h) commands in front of the erase block (60h-d0h) command. see multi-plane operations for details. erase block (60h-d0h) the erase block (60h-d0h) command erases the specified block in the nand flash array. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). to erase a block, write 60h to the command register. then write three address cycles containing the row address; the page address is ignored. conclude by writing d0h to the command register. the selected die (lun) will go busy (rdy = 0, ardy = 0) for t bers while the block is erased. to determine the progress of an erase operation, the host can monitor the target's r/ b# signal, or alternatively, the status operations (70h, 78h) can be used. when the die (lun) is ready (rdy = 1, ardy = 1) the host should check the status of the fail bit. in devices that have more than one die (lun) per target, during and following inter- leaved die (multi-lun) operations, the read status enhanced (78h) command must be used to select only one die (lun) for status output. use of the read status (70h) command could cause more than one die (lun) to respond, resulting in bus con- tention. the erase block (60h-d0h) command is used as the final command of a multi- plane erase operation. it is preceded by one or more erase block multi-plane (60h-d1h) commands. all of blocks in the addressed planes are erased. the host should check the status of the operation by using the status operations (70h, 78h). see multi- plane operations for multi-plane addressing requirements. figure 56: erase block (60h-d0h) operation cycle type dq[7:0] sr[6] command address address address command t wb t bers 60h r1 r2 r3 d0h micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand erase operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 89 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
erase block multi-plane (60h-d1h) the erase block multi-plane (60h-d1h) command queues a block in the specified plane to be erased in the nand flash array. this command can be issued one or more times. each time a new plane address is specified, that plane is also queued for a block to be erased. to specify the final block to be erased and to begin the erase operation for all previously queued planes, issue the erase block (60h-d0h) command. this command is accepted by the die (lun) when it is ready (rdy = 1, ardy = 1). to queue a block to be erased, write 60h to the command register, then write three ad- dress cycles containing the row address; the page address is ignored. conclude by writing d1h to the command register. the selected die (lun) will go busy (rdy = 0, ardy = 0) for t dbsy. to determine the progress of t dbsy, the host can monitor the target's r/b# signal, or alternatively, the status operations (70h, 78h) can be used. when the lun's status shows that it is ready (rdy = 1, ardy = 1), additional erase block multi-plane (60h- d1h) commands can be issued to queue additional planes for erase. alternatively, the erase block (60h-d0h) command can be issued to erase all of the queued blocks. for multi-plane addressing requirements for the erase block multi-plane (60h- d1h) and erase block (60h-d0h) commands, see multi-plane operations. figure 57: erase block multi-plane (60hCd1h) operation cycle type dq[7:0] rdy command address address address 60h command d1h r1 command address 60h ... r2 r3 t wb t dbsy micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand erase operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 90 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
copyback operations copyback operations make it possible to transfer data within a plane from one page to another using the cache register. this is particularly useful for block management and wear leveling. the copyback operation is a two-step process consisting of a copyback read (00h-35h) and a copyback program (85h-10h) command. to move data from one page to another on the same plane, first issue the copyback read (00h-35h) com- mand. when the die (lun) is ready (rdy = 1, ardy = 1), the host can transfer the data to a new page by issuing the copyback program (85h-10h) command. when the die (lun) is again ready (rdy = 1, ardy = 1), the host should check the fail bit to verify that this operation completed successfully. to prevent bit errors from accumulating over multiple copyback operations, it is rec- ommended that the host read the data out of the cache register after the copyback read (00h-35h) completes prior to issuing the copyback program (85h-10h) com- mand. the change read column (05h-e0h) command can be used to change the column address. the host should check the data for ecc errors and correct them. when the copyback program (85h-10h) command is issued, any corrected data can be in- put. the change row address (85h) command can be used to change the column address. it is not possible to use the copyback operation to move data from one plane to anoth- er or from one die (lun) to another. instead, use a read page (00h-30h) or copy- back read (00h-35h) command to read the data out of the nand, and then use a program page (80h-10h) command with data input to program the data to a new plane or die (lun). between the copyback read (00h-35h) and copyback program (85h-10h) com- mands, the following commands are supported: status operations (70h, 78h), and column address operations (05h-e0h, 06h-e0h, 85h). reset operations (ffh, fch) can be issued after copyback read (00h-35h), but the contents of the cache registers on the target are not valid. in devices which have more than one die (lun) per target, once the copyback read (00h-35h) is issued, interleaved die (multi-lun) operations are prohibited until after the copyback program (85h-10h) command is issued. multi-plane copyback operations multi-plane copyback read operations improve read data throughput by copying data simultaneously from more than one plane to the specified cache registers. this is done by prepending one or more read page multi-plane (00h-32h) commands in front of the copyback read (00h-35h) command. the copyback program multi-plane (85h-11h) command can be used to further system performance of copyback program operations by enabling movement of multiple pages from the cache registers to different planes of the nand flash array. this is done by prepending one or more copyback program (85h-11h) commands in front of the copyback program (85h-10h) command. see multi-plane operations for details. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand copyback operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 91 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
copyback read (00h-35h) the copyback read (00h-35h) command is functionally identical to the read page (00h-30h) command, except that 35h is written to the command register instead of 30h. see read page (00h-30h) (page 76) for further details. though it is not required, it is recommended that the host read the data out of the de- vice to verify the data prior to issuing the copyback program (85h-10h) command to prevent the propagation of data errors. figure 58: copyback read (00h-35h) operation cycle type dq[7:0] rdy command address address address address address command t wb t r t rr 00h c1 c2 r1 r2 r3 35h d out d n d out d n+1 d out d n+2 figure 59: copyback read (00hC35h) with change read column (05hCe0h) operation cycle type dq[7:0] rdy command address address address address address command t wb t r t rr 00h c1 c2 r1 r2 r3 35h 1 cycle type dq[7:0] rdy command address address command t ccs 05h c1 c2 e0h d0 dk dj + n dk + 1 dk + 2 1 d out d out d out d out d out d out micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand copyback operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 92 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
copyback program (85hC10h) the copyback program (85h-10h) command is functionally identical to the pro- gram page (80h-10h) command, except that when 85h is written to the command register, cache register contents are not cleared. see program page (80h-10h) (page 83) for further details. figure 60: copyback program (85hC10h) operation cycle type dq[7:0] rdy command address address address address address command t wb t prog 85h c1 c2 r1 r2 r3 10h figure 61: copyback program (85h-10h) with change write column (85h) operation cycle type dq[7:0] rdy command address address address address address t wb t prog 85h c1 c2 r1 r2 r3 1 cycle type dq[7:0] rdy command address address t ccs t adl 85h command 10h c1 c2 d in di dj d in d in di + 1 d in dj + 1 d in dj + 2 1 copyback read multi-plane (00h-32h) the copyback read multi-plane (00h-32h) command is functionally identical to the read page multi-plane (00h-32h) command, except that the 35h command is written as the final command. the complete command sequence for the copyback read page multi-plane is 00h-32h-00h-35h. see read page multi-plane (00h-32h) (page 81) for further details. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand copyback operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 93 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
copyback program multi-plane (85h-11h) the copyback program multi-plane (85h-11h) command is functionally identi- cal to the program page multi-plane (80h-11h) command, except that when 85h is written to the command register, cache register contents are not cleared. see pro- gram page multi-plane 80h-11h (page 87) for further details. figure 62: copyback program multi-plane (85h-11h) operation cycle type dq[7:0] rdy t adl command address address address address address 85h c1 command address 85h ... c2 r1 r2 r3 d in d in d in command d0 dn 11h t wb t dbsy micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand copyback operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 94 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
one-time programmable (otp) operations this micron nand flash device offers a protected, one-time programmable nand flash memory area. each target has a an otp area with a range of otp pages (see ta- ble 15 (page 96)); the entire range is guaranteed to be good. customers can use the otp area in any way they desire; typical uses include programming serial numbers or other data for permanent storage. the otp area leaves the factory in an erased state (all bits are 1). programming an otp page changes bits that are 1 to 0, but cannot change bits that are 0 to 1. the otp area cannot be erased, even if it is not protected. protecting the otp area prevents further programming of the pages in the otp area. enabling the otp operation mode the otp area is accessible while the otp operation mode is enabled. to enable otp operation mode, issue the set features (efh) command to feature address 90h and write 01h to p1, followed by three cycles of 00h to p2 through p4. when the target is in otp operation mode, all subsequent page read (00h-30h) and program page (80h-10h) commands are applied to the otp area. erase commands are not valid while the target is in otp operation mode. programming otp pages each page in the otp area is programming using tthe program otp page (80h-10h) command. each page can be programmed more than once, in sections, up to the maxi- mum number allowed (see nop in table 15 (page 96)). the pages in the otp area must be programmed in ascending order. if the host issues a page program (80h-10h) command to an address beyond the max- imum page-address range, the target will be busy for t obsy and the wp# status register bit will be 0, meaning that the page is write-protected. protecting the otp area to protect the otp area, issue the otp protect (80h-10h) command to the otp pro- tect page. when the otp area is protected it cannot be programmed further. it is not possible to unprotect the otp area after it has been protected. reading otp pages to read pages in the otp area, whether the otp area is protected or not, issue the page read (00h-30h) command. if the host issues the page read (00h-30h) command to an address beyond the maxi- mum page-address range, the data output will not be valid. to determine whether the target is busy during an otp operation, either monitor r/b# or use the read status (70h) command. use of the read status enhanced (78h) command is prohibited while the otp operation is in progress. returning to normal array operation mode to exit otp operation mode and return to normal array operation mode, issue the set features (efh) command to feature address 90h and write 00h to p1 through p4. if the reset (ffh) command is issued while in otp operation mode, the target will exit otp operation mode and enter normal operating mode. if the synchronous interface is active, the target will exit otp operation and enable the asynchronous interface. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand one-time programmable (otp) operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 95 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
if the synchronous reset (fch) command is issued while in the otp operation mode, the target will exit otp operation mode and the synchronous interface remains active. table 15: otp area details description value number of otp pages 30 otp protect page address 01h otp start page address 02h number of partial page programs (nop) to each otp page 4 program otp page (80h-10h) the program otp page (80h-10h) command is used to write data to the pages within the otp area. to program data in the otp area, the target must be in otp operation mode. to use the program otp page (80h-10h) command, issue the 80h command. issue five address cycles including the column address, the page address within the otp page range, and a block address of 0. next, write the data to the cache register using data input cycles. after data input is complete, issue the 10h command. r/b# goes low for the duration of the array programming time, t prog. the read sta- tus (70h) command is the only valid command for reading status in otp operation mode. the rdy bit of the status register will reflect the state of r/b#. use of the read status enhanced (78h) command is prohibited. when the target is ready, read the fail bit of the status register to determine whether the operation passed or failed (see table 14 (page 65)). the program otp page (80h-10h) command also accepts the change write col- umn (85h) command during data input. if a program page command is issued to the otp area after the area has been protec- ted, then r/b# goes low for t obsy. after t obsy, the status register is set to 60h. figure 63: program otp page (80h-10h) operation cycle type dq[7:0] r/b# t adl t whr command address address address address address 80h command 70h command 10h c1 c2 otp page 00h 00h dout din din din status d1 dn t wb t prog micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand one-time programmable (otp) operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 96 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 64: program otp page (80h-10h) with change write column (85h) operation cycle type dq[7:0] r/b# t adl command address address address address address 80h c1 c2 otp page 00h 00h din din din dn dm 1 cycle type dq[7:0] r/b# t whr command 70h command 10h command address address 85h c1 c2 dout status t ccs din din din dp dr t wb t prog 1 command 85h protect otp area (80h-10h) the protect otp area (80h-10h) command is used to prevent further programming of the pages in the otp area. the protect the otp area, the target must be in otp opera- tion mode. to protect all data in the otp area, issue the 80h command. issue five address cycles including the column address, otp protect page address and block address; the column and block addresses are fixed to 0. next, write 00h data for the first byte location and issue the 10h command. r/b# goes low for the duration of the array programming time, t prog. the read sta- tus (70h) command is the only valid command for reading status in otp operation mode. the rdy bit of the status register will reflect the state of r/b#. use of the read status enhanced (78h) command is prohibited. when the target is ready, read the fail bit of the status register to determine if the oper- ation passed or failed (see table 14 (page 65)). if the protect otp area (80h-10h) command is issued after the otp area has already been protected, r/b# goes low for t obsy. after t obsy, the status register is set to 60h. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand one-time programmable (otp) operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 97 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 65: protect otp area (80h-10h) operation cycle type dq[7:0] r/b# t adl t whr command address address address address address 80h command 70h command 10h 00h 00h 01h 00h 00h dout din status 00h t wb t prog note: 1. otp data is protected following a status confirmation. read otp page (00h-30h) the read otp page (00h-30h) command is used to read data from the pages in the otp area. to read data in the otp area, the target must be in otp operation mode. to use the read otp page (00h-30h) command, issue the 00h command. issue five address cycles including the column address, the page address within the otp page range, and a block address of 0. next, issue the 30h command. the selected die (lun) will go busy (rdy = 0, ardy = 0) for t r as data is transferred. to determine the progress of the data transfer, the host can monitor the target's r/b# signal, or alternatively the read status (70h) command can be used. if the status op- erations are used to monitor the dies (lun's) status, when the die (lun) is ready (rdy = 1, ardy = 1) the host disables status output and enables data output by issuing the read mode (00h) command. when the host requests data output, it begins at the col- umn address specified. additional pages within the otp area can be read by repeating the read otp page (00h-30h) command. the read otp page (00h-30h) command is compatible with the change read col- umn (05h-e0h) command. use of the read status enhanced (78h) and change read column enhanced (06h-e0h) commands are prohibited. figure 66: read otp page (00h-30h) operation cycle type dq[7:0] r/b# command address address address address address command t wb t r t rr 00h c1 c2 otp page 00h 00h 30h dout d n dout d n+1 dout d n+2 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand one-time programmable (otp) operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 98 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
multi-plane operations each nand flash logical unit (lun) is divided into multiple physical planes. each plane contains a cache register and a data register independent of the other planes. the planes are addressed via the low-order block address bits. specific details are provided in device and array organization. multi-plane operations make better use of the nand flash arrays on these physical planes by performing concurrent read, program, or erase operations on multiple planes, significantly improving system performance. multi-plane operations must be of the same type across the planes; for example, it is not possible to perform a program operation on one plane with an erase operation on another. when issuing multi-plane program or erase operations, use the read status (70h) command and check whether the previous operation(s) failed. if the read sta- tus (70h) command indicates that an error occurred (fail = 1 and/or failc = 1), use the read status enhanced (78h) commandtime for each planeto determine which plane operation failed. multi-plane addressing multi-plane commands require an address per operational plane. for a given multi- plane operation, these addresses are subject to the following requirements: ? the lun address bit(s) must be identical for all of the issued addresses. ? the plane select bit, ba[8], must be different for each issued address. ? the page address bits, pa[7:0], must be identical for each issued address. the read status (70h) command should be used following multi-plane pro- gram page and erase block operations on a single die (lun). micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand multi-plane operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 99 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
interleaved die (multi-lun) operations in devices that have more than one die (lun) per target, it is possible to improve per- formance by interleaving operations between the die (luns). an interleaved die (multi- lun) operation is one that is issued to an idle die (lun) (rdy = 1) while another die (lun) is busy (rdy = 0). interleaved die (multi-lun) operations are prohibited following reset (ffh, fch), iden- tification (90h, ech, edh), and configuration (eeh, efh) operations until ardy =1 for all of the die (luns) on the target. during an interleaved die (multi-lun) operation, there are two methods to determine operation completion. the r/b# signal indicates when all of the die (luns) have finish- ed their operations. r/b# remains low while any die (lun) is busy. when r/b# goes high, all of the die (luns) are idle and the operations are complete. alternatively, the read status enhanced (78h) command can report the status of each die (lun) in- dividually. if a die (lun) is performing a cache operation, like program page cache (80h-15h), then the die (lun) is able to accept the data for another cache operation when status register bit 6 is 1. all operations, including cache operations, are complete on a die when status register bit 5 is 1. use the read status enhanced (78h) command to monitor status for the ad- dressed die (lun). when multi-plane commands are used with interleaved die (multi- lun) operations, the multi-plane commands must also meet the requirements, see multi- plane operations for details. after the read status enhanced (78h) command has been issued, the read status (70h) command may be issued for the previously ad- dressed die (lun). see command definitions for the list of commands that can be issued while other die (luns) are busy. during an interleaved die (multi-lun) operation that involves a program-series (80h-10h, 80h-15h, 80h-11h) operation and a read operation, the program-series op- eration must be issued before the read-series operation. the data from the read- series operation must be output to the host before the next program-series operation is issued. this is because the 80h command clears the cache register contents of all cache registers on all planes. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand interleaved die (multi-lun) operations pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 100 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
error management each nand flash die (lun) is specified to have a minimum number of valid blocks (nvb) of the total available blocks. this means the die (luns) could have blocks that are invalid when shipped from the factory. an invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ecc. additional blocks can develop with use. however, the total number of available blocks per die (lun) will not fall below nvb during the endurance life of the product. although nand flash memory devices could contain bad blocks, they can be used quite reliably in systems that provide bad-block management and error-correction algo- rithms. this type of software environment ensures data integrity. internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the nand flash array. nand flash devices are shipped from the factory erased. the factory identifies invalid blocks before shipping by attempting to program the bad-block mark into every loca- tion in the first page of each invalid block. it may not be possible to program every location with the bad-block mark. however, the first spare area location in each bad block is guaranteed to contain the bad-block mark. this method is compliant with on- fi factory defect mapping requirements. see the following table for the first spare area location and the bad-block mark. system software should check the first spare area location on the first page of each block prior to performing any program or erase operations on the nand flash de- vice. a bad block table can then be created, enabling system software to map around these areas. factory testing is performed under worst-case conditions. because invalid blocks could be marginal, it may not be possible to recover this information if the block is erased. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over the life of the nand flash device, the following precautions are required: ? always check status after a program or erase operation ? under typical conditions, use the minimum required ecc (see table below) ? use bad-block management and wear-leveling algorithms the first block (physical block address 00h) for each ce# is guaranteed to be valid with ecc when shipped from the factory. table 16: error management details description requirement minimum number of valid blocks (nvb) per lun 3996 total available blocks per lun 4096 first spare area location byte 4096 bad-block mark 00h minimum required ecc 24-bit ecc per 1080 bytes of data micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand error management pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 101 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
output drive impedance because nand flash is designed for use in systems that are typically point-to-point con- nections, an option to control the drive strength of the output buffers is provided. drive strength should be selected based on the expected loading of the memory bus. there are four supported settings for the output drivers: overdrive 2, overdrive 1, nominal, and underdrive. the nominal output drive strength setting is the power-on default value. the host can select a different drive strength setting using the set features (efh) command. the output impedance range from minimum to maximum covers process, voltage, and temperature variations. devices are not guaranteed to be at the nominal line. table 17: output drive strength test conditions (v ccq = 1.7C1.95v) range process voltage temperature maximum fast-fast 1.95v C25c nominal typical-typical 1.8v +25c minimum slow-slow 1.7v +85c table 18: output drive strength impedance values (v ccq = 1.7C1.95v) output strength rpd/rpu v out to v ssq minimum nominal maximum unit overdrive 2 rpd v ccq 0.2 7.5 13.5 34 ohms v ccq 0.5 9 18 31 ohms v ccq 0.8 11 23.5 44 ohms rpu v ccq 0.2 11 23.5 44 ohms v ccq 0.5 9 18 31 ohms v ccq 0.8 7.5 13.5 34 ohms overdrive 1 rpd v ccq 0.2 10.5 19 47 ohms v ccq 0.5 13 25 44 ohms v ccq 0.8 16 32.5 61.5 ohms rpu v ccq 0.2 16 32.5 61.5 ohms v ccq 0.5 13 25 44 ohms v ccq 0.8 10.5 19 47 ohms nominal rpd v ccq 0.2 15 27 66.5 ohms v ccq 0.5 18 35 62.5 ohms v ccq 0.8 22 52 88 ohms rpu v ccq 0.2 22 52 88 ohms v ccq 0.5 18 35 62.5 ohms v ccq 0.8 15 27 66.5 ohms micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand output drive impedance pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 102 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 18: output drive strength impedance values (v ccq = 1.7C1.95v) (con- tinued) output strength rpd/rpu v out to v ssq minimum nominal maximum unit underdrive rpd v ccq 0.2 21.5 39 95 ohms v ccq 0.5 26 50 90 ohms v ccq 0.8 31.5 66.5 126.5 ohms rpu v ccq 0.2 31.5 66.5 126.5 ohms v ccq 0.5 26 50 90 ohms v ccq 0.8 21.5 39 95 ohms table 19: output drive strength conditions (v ccq = 2.7C3.6v) range process voltage temperature maximum fast-fast 3.6v C40c nominal typical-typical 3.3v +25c minimum slow-slow 2.7v +85c table 20: output drive strength impedance values (v ccq = 2.7C3.6v) output strength rpd/rpu v out to v ssq minimum nominal maximum unit overdrive 2 rpd v ccq x 0.2 6.0 10.0 18.0 ohms v ccq x 0.5 10.0 18.0 35.0 ohms v ccq x 0.8 15.0 25.0 49.0 ohms rpu v ccq x 0.2 15.0 25.0 49.0 ohms v ccq x 0.5 10.0 18.0 35.0 ohms v ccq x 0.8 6.0 10.0 18.0 ohms overdrive 1 rpd v ccq x 0.2 8.0 15.0 30.0 ohms v ccq x 0.5 15.0 25.0 45.0 ohms v ccq x 0.8 20.0 35.0 65.0 ohms rpu v ccq x 0.2 20.0 35.0 65.0 ohms v ccq x 0.5 15.0 25.0 45.0 ohms v ccq x 0.8 8.0 15.0 30.0 ohms nominal rpd v ccq x 0.2 12.0 22.0 40.0 ohms v ccq x 0.5 20.0 35.0 65.0 ohms v ccq x 0.8 25.0 50.0 100.0 ohms rpu v ccq x 0.2 25.0 50.0 100.0 ohms v ccq x 0.5 20.0 35.0 65.0 ohms v ccq x 0.8 12.0 22.0 40.0 ohms micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand output drive impedance pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 103 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 20: output drive strength impedance values (v ccq = 2.7C3.6v) (contin- ued) output strength rpd/rpu v out to v ssq minimum nominal maximum unit underdrive rpd v ccq x 0.2 18.0 32.0 55.0 ohms v ccq x 0.5 29.0 50.0 100.0 ohms v ccq x 0.8 40.0 75.0 150.0 ohms rpu v ccq x 0.2 40.0 75.0 150.0 ohms v ccq x 0.5 29.0 50.0 100.0 ohms v ccq x 0.8 18.0 32.0 55.0 ohms table 21: pull-up and pull-down output impedance mismatch drive strength minimum maximum unit notes overdrive 2 0 6.3 ohms 1, 2 overdrive 1 0 8.8 ohms 1, 2 nominal 0 12.3 ohms 1, 2 underdrive 0 17.5 ohms 1, 2 notes: 1. mismatch is the absolute value between pull-up and pull-down impedances. both are measured at the same temperature and voltage. 2. test conditions: v ccq = v ccq (min), v out = v ccq 0.5, t a = t oper . micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand output drive impedance pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 104 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
ac overshoot/undershoot specifications the supported ac overshoot and undershoot area depends on the timing mode selec- ted by the host. table 22: overshoot/undershoot parameters parameter timing mode unit 0 1 2 3 4 5 maximum peak amplitude provided for overshoot area 1 1 1 1 1 1 v maximum peak amplitude provided for undershoot area 1 1 1 1 1 1 v maximum overshoot area above v ccq 3 3 3 2.25 1.8 1.5 v-ns maximum undershoot area below v ssq 3 3 3 2.25 1.8 1.5 v-ns figure 67: overshoot maximum amplitude overshoot area time (ns) volts (v) v ccq figure 68: undershoot undershoot area maximum amplitude time (ns) volts (v) v ssq micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand ac overshoot/undershoot specifications pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 105 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
synchronous input slew rate though all ac timing parameters are tested with a nominal input slew rate of 1 v/ns, it is possible to run the device at a slower slew rate. the input slew rates shown below are sampled, and not 100% tested. when using slew rates slower than the minimum values, timing must be derated by the host. table 23: test conditions for input slew rate parameter value rising edge v il(dc) to v ih(ac) falling edge v ih(dc) to v il(ac) temperature range t a table 24: input slew rate (v ccq = 1.7C1.95v) command/ address and dq v/ns clk/dqs slew rate derating v ih(ac) /v il(ac) = 540mv, v ih(dc) /v il(dc) = 360mv unit 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 set hold set hold set hold set hold set hold set hold set hold set hold 1 0 0 0 0 - - - - - - - - - - - - ps 0.9 0 0 0 0 0 0 - - - - - - - - - - ps 0.8 - - 0 0 0 0 0 0 - - - - - - - - ps 0.7 - - - - 0 0 0 0 0 0 - - - - - - ps 0.6 - - - - - - 0 0 0 0 0 0 - - - - ps 0.5 - - - - - - - - 0 0 0 0 180 180 - - ps 0.4 - - - - - - - - - - 180 180 360 360 660 660 ps 0.3 - - - - - - - - - - - - 660 660 920 920 ps micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous input slew rate pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 106 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
output slew rate the output slew rate is tested using the following setup with only one die per dq channel. table 25: test conditions for output slew rate parameter value v ol(dc) 0.3 v ccq v oh(ac) 0.7 v ccq v ol(ac) 0.2 v ccq v oh(dc) 0.8 v ccq rising edge ( t rise) v ol(dc) to v oh(ac) falling edge ( t fall) v oh(dc) to v ol(ac) output capacitive load (c load ) 5pf temperature range t a table 26: output slew rate (v ccq = 1.7C1.95v) output drive strength min max unit overdrive 2 1 5.5 v/ns overdrive 1 0.85 5 v/ns nominal 0.75 4 v/ns underdrive 0.6 4 v/ns table 27: output slew rate (v ccq = 2.7C3.6v) output drive strength min max unit overdrive 2 1.5 10.0 v/ns overdrive 1 1.5 9.0 v/ns nominal 1.2 7.0 v/ns underdrive 1.0 5.5 v/ns micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand output slew rate pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 107 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
electrical specifications stresses greater than those listed can cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods can affect reliability. table 28: absolute maximum ratings by device parameter symbol min 1 max 1 unit voltage input v in -0.6 4.6 v v cc supply voltage v cc -0.6 4.6 v v ccq supply voltage v ccq -0.6 4.6 v storage temperature t stg -65 150 c note: 1. voltage on any pin relative to v ss . table 29: recommended operating conditions parameter symbol min typ max unit operating temperature commercial t a 0 C 70 c industrial C40 C 85 v cc supply voltage v cc 2.7 3.3 3.6 v v ccq supply voltage (1.8v) v ccq 1.7 1.8 1.95 v v ccq supply voltage (3.3v) 2.7 3.3 3.6 v v ss ground voltage v ss 0 0 0 v v ssq ground voltage v ssq 0 0 0 v table 30: valid blocks per lun parameter symbol min max unit notes valid block number nvb 3996 4096 blocks 1 note: 1. invalid blocks are block that contain one or more bad bits beyond ecc. the device may contain bad blocks upon shipment. additional bad blocks may develop over time; how- ever, the total number of available blocks will not drop below nvb during the endur- ance life of the device. do not erase or program blocks marked invalid from the factory. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand electrical specifications pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 108 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 31: capacitance: 100-ball bga package description symbol dual die package unit notes min typ max input capacitance (clk) c ck 3.5 4.0 4.5 pf 3 input capacitance (ale, cle, w/r#) c in 3.5 4.0 4.5 pf 3 input/output capacitance (dq[7:0], dqs) c io 4.0 4.5 5.0 pf 3 input capacitance (ce#, wp#) c other C C 5 pf delta clock capacitance dc ck C C 0.25 pf delta input capacitance dc in C C 0.5 pf delta input/output capacitance dc io C C 0.5 pf notes: 1. verified in device characterization; not 100% tested. 2. test conditions: t a = 25oc, ? = 100 mhz, v in = 0v. 3. values for c ck , c in and c io (typ) are estimates. table 32: capacitance: 48-pin tsop package description symbol device max unit notes input capacitance C ale, ce#, cle, re# we#, wp# c in single die package 10 pf 1 dual die package 14 input/output capacitance C dq[7:0], dqs c io single die package 5 pf 1 dual die package 10 note: 1. these parameters are verified in device characterization and are not 100% tested. test conditions: t c = 25c; f = 1 mhz; vin = 0v. table 33: capacitance: 52-pad lga package description symbol device max unit notes input capacitance C ale, ce#, cle, re#, we#, wp# c in dual die package 8 pf 1 quad die package 10 input/output capacitance C dq[7:0] c io dual die package 10 pf 1 quad die package 14 note: 1. these parameters are verified in device characterization and are not 100% tested. test conditions: t c = 25c; f = 1 mhz; vin = 0v. table 34: test conditions parameter value notes rising input transition v il(dc) to v ih(ac) 1 falling input transition v ih(dc) to v il(ac) 1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand electrical specifications pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 109 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 34: test conditions (continued) parameter value notes input rise and fall slew rates 1 v/ns C input and output timing levels v ccq /2 C output load: nominal output drive strength c l = 5pf 2, 3 notes: 1. the receiver will effectively switch as a result of the signal crossing the ac input level; it will remain in that status as long as the signal does not ring back above (below) the dc input low (high) level. 2. transmission line delay is assumed to be very small. 3. this test setup applies to all package configurations. electrical specifications C dc characteristics and operating conditions (asynchronous) table 35: dc characteristics and operating conditions (asynchronous interface) parameter conditions symbol min 1 typ 1 max 1 unit array read current (active) C i cc1_a C 20 50 ma array program current (active) C i cc2_a C 20 50 ma erase current (active) C i cc3_a C 20 50 ma i/o burst read current t rc = t rc (min); i out = 0ma i cc4r_a C 5 10 ma i/o burst write current t wc = t wc (min) i cc4w_a C 5 10 ma bus idle current C i cc5_a C 3 5 ma current during first reset command after power-on C i cc6 C C 10 ma standby current - v cc ce# = v ccq - 0.2v; wp# = 0v/v ccq i sb C 10 50 a standby current - v ccq ce# = v ccq - 0.2v; wp# = 0v/v ccq i sbq C 3 10 a staggered power-up current t rise = 1ms; c line = 0.1uf i st C C 10 ma note: 1. all values are per die (lun) unless otherwise specified. electrical specifications C dc characteristics and operating conditions (synchronous) table 36: dc characteristics and operating conditions (synchronous interface) parameter conditions symbol min 1 typ 1 max 1 unit array read current (active) ce# = v il ; t ck = t ck (min) i cc1_s C 25 50 ma array program current (active) t ck = t ck (min) i cc2_s C 25 50 ma erase current (active) t ck = t ck (min) i cc3_s C 25 50 ma i/o burst read current t ck = t ck (min) i cc4r_s C 10 20 ma micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand electrical specifications C dc characteristics and operating conditions (asynchronous) pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 110 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 36: dc characteristics and operating conditions (synchronous interface) (continued) parameter conditions symbol min 1 typ 1 max 1 unit i/o burst write current t ck = t ck (min) i cc4w_s C 10 20 ma bus idle current t ck = t ck (min) i cc5_s C 5 10 ma standby current - v cc ce# = v ccq - 0.2v; wp# = 0v/v ccq i sb C 10 50 a standby current - v ccq ce# = v ccq - 0.2v; wp# = 0v/v ccq i sbq C 3 10 a note: 1. all values are per die (lun) unless otherwise specified. electrical specifications C dc characteristics and operating conditions (v ccq ) table 37: dc characteristics and operating conditions (3.3v v ccq ) parameter condition symbol min typ max unit notes ac input high voltage ce#, dq[7:0], dqs, ale, cle, clk (we#), w/r# (re#), wp# v ih(ac) 0.8 v ccq C v ccq + 0.3 v ac input low voltage v il(ac) C0.3 C 0.2 v ccq v dc input high voltage dq[7:0], dqs, ale, cle, clk (we#), w/r# (re#) v ih(dc) 0.7 v ccq C v ccq + 0.3 v dc input low voltage v il(dc) C0.3 C 0.3 v ccq v input leakage current any input v in = 0v to v ccq (all other pins under test = 0v) i li C C 10 a output leakage cur- rent dq are disabled; v out = 0v to v ccq i lo C C 10 a 1 output low current (r/b#) v ol = 0.4v i ol (r/b#) 8 10 C ma 2 notes: 1. all leakage currents are per die (lun). two die (luns) have a maximum leakage current of 20a and four die (luns) have a maximum leakage current of 40a in the asynchro- nous interface. 2. dc characteristics may need to be relaxed if r/b# pull-down strength is not set to full strength. see table 14 (page 65) for additional details. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand electrical specifications C dc characteristics and operating conditions (v ccq ) pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 111 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 38: dc characteristics and operating conditions (1.8v v ccq ) parameter condition symbol min typ max unit notes ac input high voltage ce#, dq[7:0], dqs, ale, cle, clk (we#), w/r# (r/e#), wp# v ih(ac) 0.8 v ccq C v ccq + 0.3 v ac input low voltage v il(ac) C0.3 C 0.2 v ccq v dc input high voltage dq[7:0], dqs, ale, cle, clk (we#), w/r# (r/e#) v ih(dc) 0.7 v ccq C v ccq + 0.3 v dc input low voltage v il(dc) -0.3 C 0.3 v ccq v input leakage current any input v in = 0v to v ccq (all other pins under test = 0v) i li C C 10 a 1 output leakage current dq are disabled; vout = 0v to v ccq i lo C C 10 a 1 output low current (r/b#) v ol = 0.2v i ol (r/b#) 3 4 C ma note: 1. all leakage currents are per die (lun). two die (luns) have a maximum leakage current of 20a and four die (luns) have a maximum leakage current of 40a in the asynchro- nous interface. electrical specifications C ac characteristics and operating conditions (asynchronous) table 39: ac characteristics: asynchronous command, address, and data parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 unit notes min max min max min max min max min max min max clock period 100 50 35 30 25 20 ns frequency 10 20 28 33 40 50 mhz ale to data start t adl 200 C 100 C 100 C 100 C 70 C 70 C ns 1 ale hold time t alh 20 C 10 C 10 C 5 C 5 C 5 C ns ale setup time t als 50 C 25 C 15 C 10 C 10 C 10 C ns ale to re# delay t ar 25 C 10 C 10 C 10 C 10 C 10 C ns ce# access time t cea C 100 C 45 C 30 C 25 C 25 C 25 ns ce# hold time t ch 20 C 10 C 10 C 5 C 5 C 5 C ns ce# high to output high-z t chz C 100 C 50 C 50 C 50 C 30 C 30 ns 2 cle hold time t clh 20 C 10 C 10 C 5 C 5 C 5 C ns cle to re# delay t clr 20 C 10 C 10 C 10 C 10 C 10 C ns cle setup time t cls 50 C 25 C 15 C 10 C 10 C 10 C ns ce# high to output hold t coh 0 C 15 C 15 C 15 C 15 C 15 C ns ce# setup time t cs 70 C 35 C 25 C 25 C 20 C 15 C ns data hold time t dh 20 C 10 C 5 C 5 C 5 C 5 C ns data setup time t ds 40 C 20 C 15 C 10 C 10 C 7 C ns output high-z to re# low t ir 10 C 0 C 0 C 0 C 0 C 0 C ns micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand electrical specifications C ac characteristics and operating conditions (asynchronous) pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 112 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 39: ac characteristics: asynchronous command, address, and data (continued) parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 unit notes min max min max min max min max min max min max re# cycle time t rc 100 C 50 C 35 C 30 C 25 C 20 C ns re# access time t rea C 40 C 30 C 25 C 20 C 20 C 16 ns 3 re# high hold time t reh 30 C 15 C 15 C 10 C 10 C 7 C ns 3 re# high to output hold t rhoh 0 C 15 C 15 C 15 C 15 C 15 C ns 3 re# high to we# low t rhw 200 C 100 C 100 C 100 C 100 C 100 C ns re# high to output high-z t rhz C 200 C 100 C 100 C 100 C 100 C 100 ns 2, 3 re# low to output hold t rloh 0 C 0 C 0 C 0 C 5 C 5 C ns 3 re# pulse width t rp 50 C 25 C 17 C 15 C 12 C 10 C ns ready to re# low t rr 40 C 20 C 20 C 20 C 20 C 20 C ns we# high to r/b# low t wb C 200 C 100 C 100 C 100 C 100 C 100 ns 4 we# cycle time t wc 100 C 45 C 35 C 30 C 25 C 20 C ns we# high hold time t wh 30 C 15 C 15 C 10 C 10 C 7 C ns we# high to re# low t whr 120 C 80 C 80 C 60 C 60 C 60 C ns we# pulse width t wp 50 C 25 C 17 C 15 C 12 C 10 C ns wp# transition to we# low t ww 100 C 100 C 100 C 100 C 100 C 100 C ns notes: 1. timing for t adl begins in the address cycle, on the final rising edge of we# and ends with the first rising edge of we# for data input. 2. data transition is measured 200mv from steady-steady voltage with load. this parame- ter is sampled and not 100 percent tested. 3. ac characteristics may need to be relaxed if output drive strength is not set to at least nominal. 4. do not issue a new command during t wb, even if r/b# or rdy is ready. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand electrical specifications C ac characteristics and operating conditions (asynchronous) pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 113 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
electrical specifications C ac characteristics and operating conditions (synchronous) table 40: ac characteristics: synchronous command, address, and data parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 unit notes min max min max min max min max min max min max clock period 50 30 20 15 12 10 ns frequency 20 33 50 67 83 100 mhz access window of dq[7:0] from clk t ac 10 20 10 20 10 20 10 20 10 20 10 20 ns ale to data loading time t adl 100 C 100 C 70 C 70 C 70 C 70 C ns command, ad- dress data delay t cad 25 C 25 C 25 C 25 C 25 C 25 C ns 1 ale, cle, w/r# hold t calh 10 C 5 C 4 C 3 C 2.5 C 2 C ns ale, cle, w/r# setup t cals 10 C 5 C 4 C 3 C 2.5 C 2 C ns dq hold C com- mand, address t cah 10 C 5 C 4 C 3 C 2.5 C 2 C ns dq setup C com- mand, address t cas 10 C 5 C 4 C 3 C 2.5 C 2 C ns ce# hold t ch 10 C 5 C 4 C 3 C 2.5 C 2 C ns average clk cy- cle time t ck (avg) 50 100 30 50 20 30 15 20 12 15 10 12 ns 3 absolute clk cycle time, from rising edge to rising edge t ck (abs) t ck (abs) min = t ck (avg) + t jit (per) min t ck (abs) max = t ck (avg) + t jit (per) max ns clk cycle high t ckh (abs) 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 t ck 4 clk cycle low t ckl (abs) 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 t ck 4 data output end to w/r# high t ckwr t ckwr(min) = roundup[( t dqsck(max) + t ck)/ t ck] t ck ce# setup t cs 35 C 25 C 15 C 15 C 15 C 15 C ns data in hold t dh 5 C 2.5 C 1.7 C 1.3 C 1.1 C 0.8 C ns access window of dqs from clk t dqsck C 20 C 20 C 20 C 20 C 20 C 20 ns dqs, dq[7:0] driven by nand t dqsd C 18 C 18 C 18 C 18 C 18 C 18 ns micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand electrical specifications C ac characteristics and operating conditions (synchronous) pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 114 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 40: ac characteristics: synchronous command, address, and data (continued) parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 unit notes min max min max min max min max min max min max dqs, dq[7:0] to tri-state t dqshz C 20 C 20 C 20 C 20 C 20 C 20 ns 5 dqs input high pulse width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs input low pulse width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs-dq skew t dqsq C 5 C 2.5 C 1.7 C 1.3 C 1.0 C 0.85 ns data input t dqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t ck data in setup t ds 5 C 3 C 2 C 1.5 C 1.1 C 0.8 C ns dqs falling edge from clk rising C hold t dsh 0.2 C 0.2 C 0.2 C 0.2 C 0.2 C 0.2 C t ck dqs falling to clk rising C set- up t dss 0.2 C 0.2 C 0.2 C 0.2 C 0.2 C 0.2 C t ck data valid win- dow t dvw t dvw = t qh - t dqsq ns half clock peri- od t hp t hp = min( t ckh, t ckl) ns the deviation of a given t ck (abs) from a t ck (avg) t jit (per) C0.7 0.7 C0.7 0.7 C0.7 0.7 C0.6 0.6 C0.6 0.6 C0.5 0.5 ns dq-dqs hold, dqs to first dq to go nonvalid, per access t qh t qh = t hp - t qhs ns data hold skew factor t qhs C 6 C 3 C 2 C 1.5 C 1.2 C 1 ns data output to command, ad- dress, or data in- put t rhw 100 C 100 C 100 C 100 C 100 C 100 ns ready to data output t rr 20 C 20 C 20 C 20 C 20 C 20 C ns clk high to r/ b# low t wb C 100 C 100 C 100 C 100 C 100 C 100 ns command cycle to data output t whr 80 C 60 C 60 C 60 C 60 C 60 C ns dqs write pre- amble t wpre 1.5 C 1.5 C 1.5 C 1.5 C 1.5 C 1.5 C t ck micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand electrical specifications C ac characteristics and operating conditions (synchronous) pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 115 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
table 40: ac characteristics: synchronous command, address, and data (continued) parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 unit notes min max min max min max min max min max min max dqs write post- amble t wpst 1.5 C 1.5 C 1.5 C 1.5 C 1.5 C 1.5 C t ck w/r# low to data output cy- cle t wrck 20 C 20 C 20 C 20 C 20 C 20 C ns wp# transition to command cy- cle t ww 100 C 100 C 100 C 100 C 100 C 100 C ns notes: 1. delay is from start of command to next command, address, or data cycle; start of ad- dress to next command, address, or data cycle; and end of data to start of next com- mand, address, or data cycle. 2. this value is specified in the parameter page. 3. t ck(avg) is the average clock period over any consecutive 200-cycle window. 4. t ckh(abs) and t ckl(abs) include static offset and duty cycle jitter. 5. t dqshz begins when w/r# is latched high by clk. this parameter is not referenced to a specific voltage level; it specifies when the device outputs are no longer driving. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand electrical specifications C ac characteristics and operating conditions (synchronous) pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 116 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
electrical specifications C array characteristics table 41: array characteristics parameter symbol typ max unit notes number of partial page programs nop C 1 cycles 1 erase block operation time t bers 3 10 ms cache busy t cbsy 3 2200 s change column setup time to data in/out or next command t ccs C 200 ns dummy busy time t dbsy 0.5 1 s cache read busy time t rcbsy 3 50 s busy time for set features and get features operations t feat C 1 s busy time for interface change t itc C 1 s 2 last page program operation time t lprog C C s 3 busy time for otp data program operation if otp is protected t obsy C 30 s power-on reset time t por C 1 ms program page operation time t prog 1300 2200 s read page operation time t r C 50 s notes: 1. the pages in the otp block have an nop of 4. 2. t itc (max) is the busy time when the interface changes from asynchronous to synchro- nous using the set features (efh) command or synchronous to asynchronous using the reset (ffh) command. during the t itc time, any command, including read status (70h) and read status enhanced (78h), is prohibited. 3. t lprog = t prog (last page) + t prog (last page - 1) - command load time (last page) - address load time (last page) - data load time (last page). micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand electrical specifications C array characteristics pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 117 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
asynchronous interface timing diagrams figure 69: reset operation cle ce# we# r/b# dq[7:0] t rst t wb ffh reset command figure 70: reset lun operation t wb dont care fah row add 1 row add 2 row add 3 t ds t dh t wp t wp t wc t ch t als t alh t wh t cls t clh t alh t cs t rst dq[7:0] r/b# ale we# cle ce# micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 118 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 71: read status cycle re# ce# we# cle dq[7:0] t rhz t wp t whr t clr t ch t cls t cs t clh t dh t rp t chz t ds t rea t rhoh t ir 70h status output dont care t cea t coh figure 72: read status enhanced cycle t whr t ar dont care 78h row add 1 row add 2 row add 3 status output t ds t dh t wp t wp t wc t ch t als t alh t wh t cls t clh t alh t cs t cea t chz t rea t rhoh t rhz t coh dq[7:0] re# ale we# cle ce# micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 119 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 73: read parameter page we# ale cle re# r/b# ech 00h t r p0 0 p1 0 p255 0 p0 1 t wb t rr dq[7:0] t rp t rc figure 74: read page d out n d out n + 1 d out m we# ce# ale cle re# rdy dqx t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz dont care col add 1 col add 2 row add 1 row add 2 row add 3 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 120 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 75: read page operation with ce# dont care re# ce# t rea t chz t coh t cea re# ce# ale cle dqx i/ox out rdy we# data output t r dont care address (5 cycles) 00h 30h micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 121 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 76: change read column we# ce# ale cle re# rdy dqx t rhw t rc d out m d out m + 1 col add 1 col add 2 05h e0h t rea t clr d out n C 1 d out n t ccs column address m micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 122 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 77: read page cache sequential t wc we# ce# ale cle re# rdy dqx column address 0 page address m page address m column address 00h t cea t ds t clh t cls t cs t ch t dh t rr t wb t r t rc t rea 30h 31h col add 2 row add 1 row add 2 row add 3 00h t rcbsy col add 1 t rhw t clh t ch t ds t wb t cls t cs 31h 1 we# ce# ale cle re# rdy dqx column address 0 page address m t rc t rea d out 0 t rhw d out 1 dont care column address 0 t clh t ch t rea t cea t rhw t ds t rr t rcbsy t wb column address 0 3fh t cls t cs t rc d out d out 0 d out 1 d out d out 0 d out 1 d out d out 0 d out 1 d out 31h t rcbsy page address m + 1 page address m + 2 1 t dh t dh micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 123 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 78: read page cache random t wc we# ce# ale cle re# rdy dqx page address m column address 00h t ds t clh t cls t cs t ch t dh t wb t r 30h 00h col add 2 row add 1 row add 2 row add 3 00h col add 1 page address n column address 00h col add 2 row add 1 row add 2 col add 1 1 we# ce# ale cle re# rdy dqx dont care column address 0 t ch t rea t cea t rhw t ds t dh t rr t rcbsy t wb column address 0 d out 0 d out 3fh t cs t rc 31h t rcbsy d out 1 d out 0 d out d out 1 page address m page address n page address n column address 00h col add 2 row add 1 row add 2 row add 3 col add 1 1 t clh t cls micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 124 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 79: read id operation we# ce# ale cle re# dqx address, 1 cycle 90h 00h or 20h byte 2 byte 0 byte 1 byte 3 byte 4 t ar t rea t whr figure 80: program page operation we# ce# ale cle re# rdy dqx t wc t adl 1 up to m byte serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in m 70h status 10h t prog t whr t wb dont care micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 125 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 81: program page operation with ce# dont care address (5 cycles) data input 10h we# ce# t wp t ch t cs dont care data input 80h cle ce# we# ale dqx figure 82: program page operation with change write column we# ce# ale cle re# rdy dqx t wc serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in m d in n t adl t ccs change write column command column address read status command serial input 85h t prog t wb t whr dont care col add 1 col add 2 d in p d in q 70h status 10h micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 126 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 83: program page cache we# ce# ale cle re# rdy dqx 15h t cbsy t wb t wb t whr t lprog col add 1 80h 10h 70h status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page - 1 last page serial input t wc dont care 80h t adl row add 3 figure 84: program page cache ending on 15h we# ce# ale cle re# dqx 15h col add 1 80h 15h 70h status 70h status 70h status col add 2 row add 2 row add 1 row add 3 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page last page C 1 serial input t wc dont care 80h poll status until: i/o6 = 1, ready to verify successful completion of the last 2 pages: i/o5 = 1, ready i/o0 = 0, last page program successful i/o1 = 0, last page C 1 program successful t adl t whr t whr t adl micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 127 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 85: copyback we# ce# ale cle re# rdy dqx t wb t prog t wb busy busy read status command t wc dont care t adl t whr col add 2 row add 1 row add 2 70h 10h status data n row add 3 col add 1 00h col add 2 row add 1 row add 2 row add 3 35h (or 30h) col add 1 85h data 1 t r data input optional figure 86: erase block operation we# ce# ale cle re# rdy dq[7:0] read status command busy row address 60h row add 1 row add 2 row add 3 70h status d0h t wc t bers t wb t whr dont care i/o0 = 0, pass i/o0 = 1, fail micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand asynchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 128 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
synchronous interface timing diagrams figure 87: set features operation clk ce# ale cle w/r# r/b# dqx t cad efh feat addr feat addr t feat t wb dont care t cad t cs t cad p1 0 p1 1 p2 0 p2 1 p3 0 p3 1 p4 0 p4 1 dqs t cals t cals t dqss notes: 1. when ce# remains low, t cad begins at the rising edge of the clock from which the last data byte is input for the subsequent command or data input cycle(s). 2. t dsh (min) generally occurs during t dqss (min). 3. t dss (min) generally occurs during t dqss (max). 4. the cycle that t cad is measured from may be an idle cycle (as shown), another com- mand cycle, an address cycle, or a data cycle. the idle cycle is shown in this diagram for simplicity. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 129 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 88: read id operation clk ce# ale cle w/r# dq[7:0] 90h 00h or 20h t dqsd dont care t cad t cs t cad t dqshz dqs t rhw t cals t dqsck t cals driven t calh t ckwr t calh t whr byte 0 byte 0 byte 1 byte 2 byte 3 byte 3 byte 4 byte 4 byte 2 byte 1 t cals micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 130 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 89: get features operation clk ce# ale cle w/r# rdy dq[7:0] eeh t feat t dqsd t wb dont care t cad t cs t cad t dqshz dqs t rhw t cals t dqsck driven t calh t ckwr t calh t wrck feat addr p1 p2 p3 p4 t cals t cals t cals micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 131 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 90: reset (fch) operation clk ale cle dqs dq[7:0] r/b# t calh t cah t cas t cals t calh dont care t calh t cals t rst ce# t ch t cs t cad t wb w/r# fch synchronous reset command micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 132 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 91: read status cycle clk ce# ale cle w/r# rdy dq[7:0] read status command 70h t whr dont care dqs t dqsd t rhw t cad t ckwr t dqshz driven status status micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 133 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 92: read status enhanced operation clk ce# ale cle w/r# dq[7:0] 78h t whr dont care t cad t cs t cad t cad t cad dqs t dqsd t rhw t cad t ckwr t dqshz driven row add 1 row add 2 row add 3 status status micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 134 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 93: read parameter page operation clk ce# ale cle w/r# rdy dq[7:0] ech t r t dqsd t wb driven dont care t cad t cs t cad t dqshz dqs t rhw t dqsck t cals t calh t ckwr t calh t wrck 00h p1 p2 pn-3 pn-2 pn-1 pn p0 t cals t cals micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 135 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 94: read page operation clk ce# ale cle w/r# rdy dqx t cad 00h col add 1 col add 2 t r t wb dont care t cad t cs t cad t cad t cad t cad t cad dqs 30h row add 1 row add 2 row add 3 t cals driven clk ce# ale cle w/r# rdy dqx t cad 1 up to m byte serial input t r t dqsd t wb t cad t dqshz dqs 30h t rhw t cals t cals t dqsck row add 3 t cals t cals t calh t ckwr t calh t wrck dout 0 dout n-3 dout n-2 dout n-1 dout n 1 1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 136 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 95: change read column clk ce# ale cle w/r# rdy dqx dont care t cad t cad t cad dqs 05h col add 1 col add 2 e0h t dqsd d out c+1 d out d-2 d out c d out d-1 d out d t dqshz t rhw t dqsck t cals t ccs t rhw driven t cals micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 137 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 96: read page cache sequential (1 of 2) clk ce# ale cle w/r# rdy dqx t r t dqsd t wb dont care t dqshz dqs 30h t rhw t dqsck 31h t rcbsy t wb t wb 31h t rcbsy data output t dqsd driven initial read access sequential read access a sequential read access b initial read data 1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 138 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 97: read page cache sequential (2 of 2) clk ce# ale cle w/r# rdy dqx dont care dqs t rcbsy t wb t rcbsy t dqsd t dqshz t rhw t dqsck data output 3fh t dqsd t dqshz t rhw t dqsck data output driven sequential read data a sequential read data b 1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 139 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 98: read page cache random (1 of 2) clk ce# ale cle w/r# rdy dqx t r t dqsd t wb t dqshz dqs 30h t rhw t dqsck t rcbsy t wb t cad x 4 00h t wb t cad 31h t rcbsy 5 address cycles data output dont care driven t rhw t cad x 4 00h t cad 31h 5 address cycles initial read access random read access a random read access b initial read data 1 figure 99: read page cache random (2 of 2) clk ce# ale cle w/r# rdy dqx dont care dqs t cad x 4 t wb 31h t rcbsy t wb t rcbsy t dqsd t dqshz t rhw t dqsck data output 3fh t dqsd t dqshz t rhw t dqsck data output driven random read access b random read data a random read data b 1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 140 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 100: multi-plane read page (1 of 2) clk w/r# ce# ale cle rdy dqx dqs t wb t dbsy 32h or 00h t cad x 5 t cad address a 5 cycles 00h column and row addresses must be the same for all planes t wb t r t dqsd t cad x 5 06h t cad address b 5 cycles t cals e0h 00h t cad address b 5 cycles t cad x 5 30h t dqsck t rhw data a output t dqshz if data from a plane other than a is desired, a 06h-e0h command sequence is required after t r and prior to taking w/r# low. 1 2 t cals dont care driven micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 141 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 101: multi-plane read page (2 of 2) w/r# w/r# 2 3 clk ce# ale cle rdy dqx dqs e0h t dqsd t dqshz t dqsck data b output 06h t cad address a 5 cycles t rhw t cad x 5 e0h t dqsd t dqsck 3 clk ce# ale cle rdy dqx dqs t dqshz t dqsck data a output 06h t cad address b 5 cycles t rhw t cad x 5 e0h t dqsd t dqshz t dqsck data b output t rhw dont care undefined (driven by nand) t ccs t ccs micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 142 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 102: program page operation (1 of 2) clk ce# ale cle w/r# rdy dqx t adl 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n+1 d in m-2 t cad t cs t cad t cad t cad t cad t cad d in n d in m-1 d in m dqs t cals t cals t dqss dont care driven 1 figure 103: program page operation (2 of 2) dont care driven clk ce# ale cle w/r# rdy dqx read status command d in n+1 d in m-2 70h 10h t prog t whr t wb d in n d in m-1 d in m t cad dqs t cals t dqss t dqsd t rhw t cad t ckwr t dqshz status status 1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 143 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 104: change write column clk ce# ale cle w/r# rdy dqx t ccs 85h col add 1 col add 2 din c+1 t cad t cad t cad din c dqs t dqss d in n+1 d in m-2 d in m-1 d in m t cals dont care driven t cals 1 clk ce# ale cle w/r# rdy dqx t ccs 85h col add 1 col add 2 d in c+1 d in d-2 t cad t cad t cad d in c d in d-1 d in d dqs t dqss t cad t cals t cals 1 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 144 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 105: multi-plane program page clk ce# ale cle w/r# rdy dqx dqs 80h t cad t cad t cad x 4 + t adl address a 5 cycles t dqss 11h t cad data a t cals t cals t dbsy t wb 80h t cad clk ce# ale cle w/r# rdy dqx dqs t cad x 4 + t adl t dqss 1 1 address b 5 cycles 70h 10h t prog t whr t wb t cad t dqsd t cad t rhw t dqshz status status data b address b 5 cycles micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 145 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 106: erase block clk ce# ale cle w/r# rdy dq[7:0] t cad 60h t bers t wb dont care t cad t cs t cad t cad t cad dqs d0h row add 1 row add 2 row add 3 read status command 70h t whr status status t dqsd t dqshz t rhw t cad driven figure 107: copyback (1 of 3) clk ce# ale cle w/r# rdy dqx dqs t cad x 5 00h t wb t cad 35h or 30h t r 5 address cycles t dqsd t dqshz t dqsck data output 05h t cad t cadx2 e0h 2 address cycles t rhw 1 dont care driven micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 146 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 108: copyback (2 of 3) clk ce# ale cle w/r# rdy dqx dqs h t dqsd data output t dqsck t rhw t dqshz t cad x 5 85h t cad 5 address cycles 85h t cad t cad + t adl 2 address cycles data t cals t cals t dqss 1 2 dont care driven figure 109: copyback (3 of 3) clk ce# ale cle w/r# rdy dqx dqs 70h 10h t prog t whr t wb dont care t cad status status t dqsd t dqshz t cad t rhw driven 2 micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 147 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 110: read otp page clk ce# ale cle w/r# r/b# dqx t cad 00h col add 1 col add 2 t r t dqsd t wb dont care t cad t cs t cad t cad t cad t cad t cad d out 0 d out n t dqshz dqs 30h t rhw t cals t cals t dqsck t cals t cals d out n-1 driven d out n-2 d out n-3 t calh t ckwr t calh 00h 00h otp page 1 t wrck micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 148 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 111: program otp page (1 of 2) clk ce# ale cle w/r# rdy dqx t adl 80h col add 1 col add 2 d in n+1 d in m-2 dont care t cad t cs t cad t cad t cad t cad t cad d in n d in m-1 d in m dqs t cals t cals t dqss 00h 00h otp page 1 driven 1 figure 112: program otp page (2 of 2) dont care driven transitioning clk ce# ale cle w/r# rdy dqx read status command d in m-2 70h 10h t prog t whr t wb d in m-1 d in m t cad dqs t cals t dqsd t rhw t cad t ckwr otp data written (following "pass" status confirmation) t dqshz 1 status status micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 149 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
figure 113: protect otp area clk ce# ale cle w/r# rdy dq[7:0] 80h col 00h col 00h 00h t dqss t cad t cad t cad t cad t cad t cad t adl dqs 00h 01h 00h dont care driven transitioning clk ce# ale cle w/r# rdy dq[7:0] read status command 70h 10h t prog t whr t wb t cad dqs t dqsd t dqshz t rhw t cad status status 1 1 t cals t cals micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand synchronous interface timing diagrams pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 150 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://
revision history rev. a C 3/10 ? initial release 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains initial descriptions of products still under development. micron confidential and proprietary advance 32gb, 64gb, 128gb asynchronous/synchronous nand revision history pdf: 09005aef83f64350 l73a_32g_64g_128g_asyncsync_nand.pdf C rev. a 3/10 en 151 micron technology, inc. reserves the right to change products or specifications without notice. ? 2010 micron technology, inc. all rights reserved. draft 03/25/10 free datasheet http://

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